Clock management tile
TODO: describe this madness
Tile CMT
Cells: 56
Switchbox SPEC_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[20].GCLK_CMT[0] | CELL[20].GCLK[0] | HCLK[26][29] |
| CELL[20].GCLK_CMT[1] | CELL[20].GCLK[1] | HCLK[32][22] |
| CELL[20].GCLK_CMT[2] | CELL[20].GCLK[2] | HCLK[26][28] |
| CELL[20].GCLK_CMT[3] | CELL[20].GCLK[3] | HCLK[32][23] |
| CELL[20].GCLK_CMT[4] | CELL[20].GCLK[4] | HCLK[26][27] |
| CELL[20].GCLK_CMT[5] | CELL[20].GCLK[5] | HCLK[32][24] |
| CELL[20].GCLK_CMT[6] | CELL[20].GCLK[6] | HCLK[26][26] |
| CELL[20].GCLK_CMT[7] | CELL[20].GCLK[7] | HCLK[32][25] |
| CELL[20].GCLK_CMT[8] | CELL[20].GCLK[8] | HCLK[26][25] |
| CELL[20].GCLK_CMT[9] | CELL[20].GCLK[9] | HCLK[32][26] |
| CELL[20].GCLK_CMT[10] | CELL[20].GCLK[10] | HCLK[26][24] |
| CELL[20].GCLK_CMT[11] | CELL[20].GCLK[11] | HCLK[32][27] |
| CELL[20].GCLK_CMT[12] | CELL[20].GCLK[12] | HCLK[26][23] |
| CELL[20].GCLK_CMT[13] | CELL[20].GCLK[13] | HCLK[32][28] |
| CELL[20].GCLK_CMT[14] | CELL[20].GCLK[14] | HCLK[26][22] |
| CELL[20].GCLK_CMT[15] | CELL[20].GCLK[15] | HCLK[32][29] |
| CELL[20].GCLK_CMT[16] | CELL[20].GCLK[16] | HCLK[26][14] |
| CELL[20].GCLK_CMT[17] | CELL[20].GCLK[17] | HCLK[32][21] |
| CELL[20].GCLK_CMT[18] | CELL[20].GCLK[18] | HCLK[26][15] |
| CELL[20].GCLK_CMT[19] | CELL[20].GCLK[19] | HCLK[32][20] |
| CELL[20].GCLK_CMT[20] | CELL[20].GCLK[20] | HCLK[26][16] |
| CELL[20].GCLK_CMT[21] | CELL[20].GCLK[21] | HCLK[32][19] |
| CELL[20].GCLK_CMT[22] | CELL[20].GCLK[22] | HCLK[26][17] |
| CELL[20].GCLK_CMT[23] | CELL[20].GCLK[23] | HCLK[32][18] |
| CELL[20].GCLK_CMT[24] | CELL[20].GCLK[24] | HCLK[26][18] |
| CELL[20].GCLK_CMT[25] | CELL[20].GCLK[25] | HCLK[32][17] |
| CELL[20].GCLK_CMT[26] | CELL[20].GCLK[26] | HCLK[26][19] |
| CELL[20].GCLK_CMT[27] | CELL[20].GCLK[27] | HCLK[32][16] |
| CELL[20].GCLK_CMT[28] | CELL[20].GCLK[28] | HCLK[26][20] |
| CELL[20].GCLK_CMT[29] | CELL[20].GCLK[29] | HCLK[32][15] |
| CELL[20].GCLK_CMT[30] | CELL[20].GCLK[30] | HCLK[26][21] |
| CELL[20].GCLK_CMT[31] | CELL[20].GCLK[31] | HCLK[32][14] |
| CELL[20].BUFH_INT_W[0] | CELL[19].IMUX_CLK[0] | HCLK[26][30] |
| CELL[20].BUFH_INT_W[1] | CELL[19].IMUX_CLK[1] | HCLK[26][31] |
| CELL[20].BUFH_INT_E[0] | CELL[20].IMUX_CLK[0] | HCLK[32][30] |
| CELL[20].BUFH_INT_E[1] | CELL[20].IMUX_CLK[1] | HCLK[32][31] |
| CELL[20].GCLK_TEST_IN[0] | CELL[20].GCLK_CMT[0] | MAIN[19][27][14] |
| CELL[20].GCLK_TEST_IN[1] | CELL[20].GCLK_CMT[1] | MAIN[19][28][14] |
| CELL[20].GCLK_TEST_IN[2] | CELL[20].GCLK_CMT[2] | MAIN[19][32][14] |
| CELL[20].GCLK_TEST_IN[3] | CELL[20].GCLK_CMT[3] | MAIN[19][31][14] |
| CELL[20].GCLK_TEST_IN[4] | CELL[20].GCLK_CMT[4] | MAIN[19][27][30] |
| CELL[20].GCLK_TEST_IN[5] | CELL[20].GCLK_CMT[5] | MAIN[19][28][30] |
| CELL[20].GCLK_TEST_IN[6] | CELL[20].GCLK_CMT[6] | MAIN[19][32][30] |
| CELL[20].GCLK_TEST_IN[7] | CELL[20].GCLK_CMT[7] | MAIN[19][31][30] |
| CELL[20].GCLK_TEST_IN[8] | CELL[20].GCLK_CMT[8] | MAIN[19][27][46] |
| CELL[20].GCLK_TEST_IN[9] | CELL[20].GCLK_CMT[9] | MAIN[19][28][46] |
| CELL[20].GCLK_TEST_IN[10] | CELL[20].GCLK_CMT[10] | MAIN[19][32][46] |
| CELL[20].GCLK_TEST_IN[11] | CELL[20].GCLK_CMT[11] | MAIN[19][31][46] |
| CELL[20].GCLK_TEST_IN[12] | CELL[20].GCLK_CMT[12] | MAIN[19][27][62] |
| CELL[20].GCLK_TEST_IN[13] | CELL[20].GCLK_CMT[13] | MAIN[19][28][62] |
| CELL[20].GCLK_TEST_IN[14] | CELL[20].GCLK_CMT[14] | MAIN[19][32][62] |
| CELL[20].GCLK_TEST_IN[15] | CELL[20].GCLK_CMT[15] | MAIN[19][31][62] |
| CELL[20].GCLK_TEST_IN[16] | CELL[20].GCLK_CMT[16] | MAIN[20][27][14] |
| CELL[20].GCLK_TEST_IN[17] | CELL[20].GCLK_CMT[17] | MAIN[20][28][14] |
| CELL[20].GCLK_TEST_IN[18] | CELL[20].GCLK_CMT[18] | MAIN[20][32][14] |
| CELL[20].GCLK_TEST_IN[19] | CELL[20].GCLK_CMT[19] | MAIN[20][31][14] |
| CELL[20].GCLK_TEST_IN[20] | CELL[20].GCLK_CMT[20] | MAIN[20][27][30] |
| CELL[20].GCLK_TEST_IN[21] | CELL[20].GCLK_CMT[21] | MAIN[20][28][30] |
| CELL[20].GCLK_TEST_IN[22] | CELL[20].GCLK_CMT[22] | MAIN[20][32][30] |
| CELL[20].GCLK_TEST_IN[23] | CELL[20].GCLK_CMT[23] | MAIN[20][31][30] |
| CELL[20].GCLK_TEST_IN[24] | CELL[20].GCLK_CMT[24] | MAIN[20][27][46] |
| CELL[20].GCLK_TEST_IN[25] | CELL[20].GCLK_CMT[25] | MAIN[20][28][46] |
| CELL[20].GCLK_TEST_IN[26] | CELL[20].GCLK_CMT[26] | MAIN[20][32][46] |
| CELL[20].GCLK_TEST_IN[27] | CELL[20].GCLK_CMT[27] | MAIN[20][31][46] |
| CELL[20].GCLK_TEST_IN[28] | CELL[20].GCLK_CMT[28] | MAIN[20][27][62] |
| CELL[20].GCLK_TEST_IN[29] | CELL[20].GCLK_CMT[29] | MAIN[20][28][62] |
| CELL[20].GCLK_TEST_IN[30] | CELL[20].GCLK_CMT[30] | MAIN[20][32][62] |
| CELL[20].GCLK_TEST_IN[31] | CELL[20].GCLK_CMT[31] | MAIN[20][31][62] |
| CELL[20].CCIO_CMT_W[0] | IO_W[1].OUT_CLKPAD | HCLK[28][24] |
| CELL[20].CCIO_CMT_W[1] | IO_W[3].OUT_CLKPAD | HCLK[28][25] |
| CELL[20].CCIO_CMT_W[2] | IO_W[5].OUT_CLKPAD | HCLK[28][26] |
| CELL[20].CCIO_CMT_W[3] | IO_W[7].OUT_CLKPAD | HCLK[28][27] |
| CELL[20].CCIO_CMT_E[0] | IO_E[1].OUT_CLKPAD | HCLK[30][24] |
| CELL[20].CCIO_CMT_E[1] | IO_E[3].OUT_CLKPAD | HCLK[30][25] |
| CELL[20].CCIO_CMT_E[2] | IO_E[5].OUT_CLKPAD | HCLK[30][26] |
| CELL[20].CCIO_CMT_E[3] | IO_E[7].OUT_CLKPAD | HCLK[30][27] |
| CELL[20].MGT_CMT_W[0] | IO_W[4].MGT_ROW[0] | HCLK[28][14] |
| CELL[20].MGT_CMT_W[1] | IO_W[4].MGT_ROW[1] | HCLK[28][15] |
| CELL[20].MGT_CMT_W[2] | IO_W[4].MGT_ROW[2] | HCLK[28][16] |
| CELL[20].MGT_CMT_W[3] | IO_W[4].MGT_ROW[3] | HCLK[28][17] |
| CELL[20].MGT_CMT_W[4] | IO_W[4].MGT_ROW[4] | HCLK[28][22] |
| CELL[20].MGT_CMT_W[5] | IO_W[4].MGT_ROW[5] | HCLK[28][23] |
| CELL[20].MGT_CMT_W[6] | IO_W[4].MGT_ROW[6] | HCLK[28][28] |
| CELL[20].MGT_CMT_W[7] | IO_W[4].MGT_ROW[7] | HCLK[28][29] |
| CELL[20].MGT_CMT_W[8] | IO_W[4].MGT_ROW[8] | HCLK[28][30] |
| CELL[20].MGT_CMT_W[9] | IO_W[4].MGT_ROW[9] | HCLK[28][31] |
| CELL[20].MGT_CMT_E[0] | IO_E[4].MGT_ROW[0] | HCLK[30][14] |
| CELL[20].MGT_CMT_E[1] | IO_E[4].MGT_ROW[1] | HCLK[30][15] |
| CELL[20].MGT_CMT_E[2] | IO_E[4].MGT_ROW[2] | HCLK[30][16] |
| CELL[20].MGT_CMT_E[3] | IO_E[4].MGT_ROW[3] | HCLK[30][17] |
| CELL[20].MGT_CMT_E[4] | IO_E[4].MGT_ROW[4] | HCLK[30][22] |
| CELL[20].MGT_CMT_E[5] | IO_E[4].MGT_ROW[5] | HCLK[30][23] |
| CELL[20].MGT_CMT_E[6] | IO_E[4].MGT_ROW[6] | HCLK[30][28] |
| CELL[20].MGT_CMT_E[7] | IO_E[4].MGT_ROW[7] | HCLK[30][29] |
| CELL[20].MGT_CMT_E[8] | IO_E[4].MGT_ROW[8] | HCLK[30][30] |
| CELL[20].MGT_CMT_E[9] | IO_E[4].MGT_ROW[9] | HCLK[30][31] |
| CELL[20].HCLK_CMT_W[0] | IO_W[4].HCLK_ROW[0] | HCLK[29][20] |
| CELL[20].HCLK_CMT_W[1] | IO_W[4].HCLK_ROW[1] | HCLK[29][21] |
| CELL[20].HCLK_CMT_W[2] | IO_W[4].HCLK_ROW[2] | HCLK[29][22] |
| CELL[20].HCLK_CMT_W[3] | IO_W[4].HCLK_ROW[3] | HCLK[29][23] |
| CELL[20].HCLK_CMT_W[4] | IO_W[4].HCLK_ROW[4] | HCLK[29][24] |
| CELL[20].HCLK_CMT_W[5] | IO_W[4].HCLK_ROW[5] | HCLK[29][25] |
| CELL[20].HCLK_CMT_W[6] | IO_W[4].HCLK_ROW[6] | HCLK[29][26] |
| CELL[20].HCLK_CMT_W[7] | IO_W[4].HCLK_ROW[7] | HCLK[29][27] |
| CELL[20].HCLK_CMT_W[8] | IO_W[4].HCLK_ROW[8] | HCLK[29][28] |
| CELL[20].HCLK_CMT_W[9] | IO_W[4].HCLK_ROW[9] | HCLK[29][29] |
| CELL[20].HCLK_CMT_W[10] | IO_W[4].HCLK_ROW[10] | HCLK[29][30] |
| CELL[20].HCLK_CMT_W[11] | IO_W[4].HCLK_ROW[11] | HCLK[29][31] |
| CELL[20].HCLK_CMT_E[0] | IO_E[4].HCLK_ROW[0] | HCLK[31][20] |
| CELL[20].HCLK_CMT_E[1] | IO_E[4].HCLK_ROW[1] | HCLK[31][21] |
| CELL[20].HCLK_CMT_E[2] | IO_E[4].HCLK_ROW[2] | HCLK[31][22] |
| CELL[20].HCLK_CMT_E[3] | IO_E[4].HCLK_ROW[3] | HCLK[31][23] |
| CELL[20].HCLK_CMT_E[4] | IO_E[4].HCLK_ROW[4] | HCLK[31][24] |
| CELL[20].HCLK_CMT_E[5] | IO_E[4].HCLK_ROW[5] | HCLK[31][25] |
| CELL[20].HCLK_CMT_E[6] | IO_E[4].HCLK_ROW[6] | HCLK[31][26] |
| CELL[20].HCLK_CMT_E[7] | IO_E[4].HCLK_ROW[7] | HCLK[31][27] |
| CELL[20].HCLK_CMT_E[8] | IO_E[4].HCLK_ROW[8] | HCLK[31][28] |
| CELL[20].HCLK_CMT_E[9] | IO_E[4].HCLK_ROW[9] | HCLK[31][29] |
| CELL[20].HCLK_CMT_E[10] | IO_E[4].HCLK_ROW[10] | HCLK[31][30] |
| CELL[20].HCLK_CMT_E[11] | IO_E[4].HCLK_ROW[11] | HCLK[31][31] |
| CELL[20].RCLK_CMT_W[0] | IO_W[4].RCLK_ROW[0] | HCLK[29][14] |
| CELL[20].RCLK_CMT_W[1] | IO_W[4].RCLK_ROW[1] | HCLK[29][15] |
| CELL[20].RCLK_CMT_W[2] | IO_W[4].RCLK_ROW[2] | HCLK[29][16] |
| CELL[20].RCLK_CMT_W[3] | IO_W[4].RCLK_ROW[3] | HCLK[29][17] |
| CELL[20].RCLK_CMT_W[4] | IO_W[4].RCLK_ROW[4] | HCLK[29][18] |
| CELL[20].RCLK_CMT_W[5] | IO_W[4].RCLK_ROW[5] | HCLK[29][19] |
| CELL[20].RCLK_CMT_E[0] | IO_E[4].RCLK_ROW[0] | HCLK[31][14] |
| CELL[20].RCLK_CMT_E[1] | IO_E[4].RCLK_ROW[1] | HCLK[31][15] |
| CELL[20].RCLK_CMT_E[2] | IO_E[4].RCLK_ROW[2] | HCLK[31][16] |
| CELL[20].RCLK_CMT_E[3] | IO_E[4].RCLK_ROW[3] | HCLK[31][17] |
| CELL[20].RCLK_CMT_E[4] | IO_E[4].RCLK_ROW[4] | HCLK[31][18] |
| CELL[20].RCLK_CMT_E[5] | IO_E[4].RCLK_ROW[5] | HCLK[31][19] |
| CELL[20].GIOB_CMT[0] | CELL[20].GIOB[0] | HCLK[28][18] |
| CELL[20].GIOB_CMT[1] | CELL[20].GIOB[1] | HCLK[30][18] |
| CELL[20].GIOB_CMT[2] | CELL[20].GIOB[2] | HCLK[28][19] |
| CELL[20].GIOB_CMT[3] | CELL[20].GIOB[3] | HCLK[30][19] |
| CELL[20].GIOB_CMT[4] | CELL[20].GIOB[4] | HCLK[28][20] |
| CELL[20].GIOB_CMT[5] | CELL[20].GIOB[5] | HCLK[30][20] |
| CELL[20].GIOB_CMT[6] | CELL[20].GIOB[6] | HCLK[28][21] |
| CELL[20].GIOB_CMT[7] | CELL[20].GIOB[7] | HCLK[30][21] |
| IO_W[4].PERF_ROW[0] | CELL[20].OMUX_PLL_PERF_S[0] | MAIN[17][26][54] |
| IO_W[4].PERF_ROW[0] | CELL[20].OMUX_PLL_PERF_N[0] | MAIN[22][26][9] |
| IO_W[4].PERF_ROW[1] | CELL[20].OMUX_PLL_PERF_S[1] | MAIN[17][26][52] |
| IO_W[4].PERF_ROW[1] | CELL[20].OMUX_PLL_PERF_N[1] | MAIN[22][26][11] |
| IO_W[4].PERF_ROW[2] | CELL[20].OMUX_PLL_PERF_S[2] | MAIN[17][26][50] |
| IO_W[4].PERF_ROW[2] | CELL[20].OMUX_PLL_PERF_N[2] | MAIN[22][26][13] |
| IO_W[4].PERF_ROW[3] | CELL[20].OMUX_PLL_PERF_S[3] | MAIN[17][26][48] |
| IO_W[4].PERF_ROW[3] | CELL[20].OMUX_PLL_PERF_N[3] | MAIN[22][26][15] |
| IO_W[4].PERF_ROW_OUTER[0] | CELL[20].OMUX_PLL_PERF_S[1] | MAIN[17][27][52] |
| IO_W[4].PERF_ROW_OUTER[0] | CELL[20].OMUX_PLL_PERF_N[1] | MAIN[22][27][11] |
| IO_W[4].PERF_ROW_OUTER[1] | CELL[20].OMUX_PLL_PERF_S[0] | MAIN[17][27][54] |
| IO_W[4].PERF_ROW_OUTER[1] | CELL[20].OMUX_PLL_PERF_N[0] | MAIN[22][27][9] |
| IO_W[4].PERF_ROW_OUTER[2] | CELL[20].OMUX_PLL_PERF_S[3] | MAIN[17][27][48] |
| IO_W[4].PERF_ROW_OUTER[2] | CELL[20].OMUX_PLL_PERF_N[3] | MAIN[22][27][15] |
| IO_W[4].PERF_ROW_OUTER[3] | CELL[20].OMUX_PLL_PERF_S[2] | MAIN[17][27][50] |
| IO_W[4].PERF_ROW_OUTER[3] | CELL[20].OMUX_PLL_PERF_N[2] | MAIN[22][27][13] |
| IO_E[4].PERF_ROW[0] | CELL[20].OMUX_PLL_PERF_S[0] | MAIN[17][27][55] |
| IO_E[4].PERF_ROW[0] | CELL[20].OMUX_PLL_PERF_N[0] | MAIN[22][27][8] |
| IO_E[4].PERF_ROW[1] | CELL[20].OMUX_PLL_PERF_S[1] | MAIN[17][27][53] |
| IO_E[4].PERF_ROW[1] | CELL[20].OMUX_PLL_PERF_N[1] | MAIN[22][27][10] |
| IO_E[4].PERF_ROW[2] | CELL[20].OMUX_PLL_PERF_S[2] | MAIN[17][27][51] |
| IO_E[4].PERF_ROW[2] | CELL[20].OMUX_PLL_PERF_N[2] | MAIN[22][27][12] |
| IO_E[4].PERF_ROW[3] | CELL[20].OMUX_PLL_PERF_S[3] | MAIN[17][27][49] |
| IO_E[4].PERF_ROW[3] | CELL[20].OMUX_PLL_PERF_N[3] | MAIN[22][27][14] |
| IO_E[4].PERF_ROW_OUTER[0] | CELL[20].OMUX_PLL_PERF_S[1] | MAIN[17][26][53] |
| IO_E[4].PERF_ROW_OUTER[0] | CELL[20].OMUX_PLL_PERF_N[1] | MAIN[22][26][10] |
| IO_E[4].PERF_ROW_OUTER[1] | CELL[20].OMUX_PLL_PERF_S[0] | MAIN[17][26][55] |
| IO_E[4].PERF_ROW_OUTER[1] | CELL[20].OMUX_PLL_PERF_N[0] | MAIN[22][26][8] |
| IO_E[4].PERF_ROW_OUTER[2] | CELL[20].OMUX_PLL_PERF_S[3] | MAIN[17][26][49] |
| IO_E[4].PERF_ROW_OUTER[2] | CELL[20].OMUX_PLL_PERF_N[3] | MAIN[22][26][14] |
| IO_E[4].PERF_ROW_OUTER[3] | CELL[20].OMUX_PLL_PERF_S[2] | MAIN[17][26][51] |
| IO_E[4].PERF_ROW_OUTER[3] | CELL[20].OMUX_PLL_PERF_N[2] | MAIN[22][26][12] |
| Destination | Source | Bit |
|---|---|---|
| CELL[20].GCLK_TEST[0] | CELL[20].GCLK_TEST_IN[0] | MAIN[19][27][0] |
| CELL[20].GCLK_TEST[1] | CELL[20].GCLK_TEST_IN[1] | MAIN[19][28][0] |
| CELL[20].GCLK_TEST[2] | CELL[20].GCLK_TEST_IN[2] | MAIN[19][32][0] |
| CELL[20].GCLK_TEST[3] | CELL[20].GCLK_TEST_IN[3] | MAIN[19][31][0] |
| CELL[20].GCLK_TEST[4] | CELL[20].GCLK_TEST_IN[4] | MAIN[19][27][16] |
| CELL[20].GCLK_TEST[5] | CELL[20].GCLK_TEST_IN[5] | MAIN[19][28][16] |
| CELL[20].GCLK_TEST[6] | CELL[20].GCLK_TEST_IN[6] | MAIN[19][32][16] |
| CELL[20].GCLK_TEST[7] | CELL[20].GCLK_TEST_IN[7] | MAIN[19][31][16] |
| CELL[20].GCLK_TEST[8] | CELL[20].GCLK_TEST_IN[8] | MAIN[19][27][32] |
| CELL[20].GCLK_TEST[9] | CELL[20].GCLK_TEST_IN[9] | MAIN[19][28][32] |
| CELL[20].GCLK_TEST[10] | CELL[20].GCLK_TEST_IN[10] | MAIN[19][32][32] |
| CELL[20].GCLK_TEST[11] | CELL[20].GCLK_TEST_IN[11] | MAIN[19][31][32] |
| CELL[20].GCLK_TEST[12] | CELL[20].GCLK_TEST_IN[12] | MAIN[19][27][48] |
| CELL[20].GCLK_TEST[13] | CELL[20].GCLK_TEST_IN[13] | MAIN[19][28][48] |
| CELL[20].GCLK_TEST[14] | CELL[20].GCLK_TEST_IN[14] | MAIN[19][32][48] |
| CELL[20].GCLK_TEST[15] | CELL[20].GCLK_TEST_IN[15] | MAIN[19][31][48] |
| CELL[20].GCLK_TEST[16] | CELL[20].GCLK_TEST_IN[16] | MAIN[20][27][0] |
| CELL[20].GCLK_TEST[17] | CELL[20].GCLK_TEST_IN[17] | MAIN[20][28][0] |
| CELL[20].GCLK_TEST[18] | CELL[20].GCLK_TEST_IN[18] | MAIN[20][32][0] |
| CELL[20].GCLK_TEST[19] | CELL[20].GCLK_TEST_IN[19] | MAIN[20][31][0] |
| CELL[20].GCLK_TEST[20] | CELL[20].GCLK_TEST_IN[20] | MAIN[20][27][16] |
| CELL[20].GCLK_TEST[21] | CELL[20].GCLK_TEST_IN[21] | MAIN[20][28][16] |
| CELL[20].GCLK_TEST[22] | CELL[20].GCLK_TEST_IN[22] | MAIN[20][32][16] |
| CELL[20].GCLK_TEST[23] | CELL[20].GCLK_TEST_IN[23] | MAIN[20][31][16] |
| CELL[20].GCLK_TEST[24] | CELL[20].GCLK_TEST_IN[24] | MAIN[20][27][32] |
| CELL[20].GCLK_TEST[25] | CELL[20].GCLK_TEST_IN[25] | MAIN[20][28][32] |
| CELL[20].GCLK_TEST[26] | CELL[20].GCLK_TEST_IN[26] | MAIN[20][32][32] |
| CELL[20].GCLK_TEST[27] | CELL[20].GCLK_TEST_IN[27] | MAIN[20][31][32] |
| CELL[20].GCLK_TEST[28] | CELL[20].GCLK_TEST_IN[28] | MAIN[20][27][48] |
| CELL[20].GCLK_TEST[29] | CELL[20].GCLK_TEST_IN[29] | MAIN[20][28][48] |
| CELL[20].GCLK_TEST[30] | CELL[20].GCLK_TEST_IN[30] | MAIN[20][32][48] |
| CELL[20].GCLK_TEST[31] | CELL[20].GCLK_TEST_IN[31] | MAIN[20][31][48] |
| CELL[20].BUFH_TEST_W | CELL[20].BUFH_TEST_W_IN | MAIN[19][30][48] |
| CELL[20].BUFH_TEST_E | CELL[20].BUFH_TEST_E_IN | MAIN[20][30][0] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][26][7] | MAIN[19][26][5] | MAIN[19][26][3] | MAIN[19][26][4] | MAIN[19][27][4] | MAIN[19][27][5] | MAIN[19][27][7] | MAIN[19][27][6] | MAIN[19][26][6] | MAIN[19][27][8] | MAIN[19][26][8] | MAIN[19][26][10] | MAIN[19][27][11] | MAIN[19][26][12] | MAIN[19][27][13] | MAIN[19][26][14] | MAIN[19][27][15] | MAIN[19][26][2] | CELL[20].IMUX_BUFG_O[0] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][29][7] | MAIN[19][29][5] | MAIN[19][29][3] | MAIN[19][29][4] | MAIN[19][28][4] | MAIN[19][28][5] | MAIN[19][28][7] | MAIN[19][28][6] | MAIN[19][29][6] | MAIN[19][28][8] | MAIN[19][29][8] | MAIN[19][29][10] | MAIN[19][28][11] | MAIN[19][29][12] | MAIN[19][28][13] | MAIN[19][28][15] | MAIN[19][29][14] | MAIN[19][27][3] | CELL[20].IMUX_BUFG_O[1] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][33][7] | MAIN[19][33][5] | MAIN[19][33][3] | MAIN[19][33][4] | MAIN[19][32][4] | MAIN[19][32][5] | MAIN[19][32][7] | MAIN[19][32][6] | MAIN[19][33][6] | MAIN[19][32][8] | MAIN[19][33][8] | MAIN[19][33][10] | MAIN[19][32][11] | MAIN[19][33][12] | MAIN[19][32][13] | MAIN[19][32][15] | MAIN[19][33][14] | MAIN[19][31][3] | CELL[20].IMUX_BUFG_O[2] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][30][7] | MAIN[19][30][5] | MAIN[19][30][3] | MAIN[19][30][4] | MAIN[19][31][4] | MAIN[19][31][5] | MAIN[19][31][7] | MAIN[19][31][6] | MAIN[19][30][6] | MAIN[19][31][8] | MAIN[19][30][8] | MAIN[19][30][10] | MAIN[19][31][11] | MAIN[19][30][12] | MAIN[19][31][13] | MAIN[19][30][14] | MAIN[19][31][15] | MAIN[19][30][2] | CELL[20].IMUX_BUFG_O[3] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][26][23] | MAIN[19][26][21] | MAIN[19][26][19] | MAIN[19][26][20] | MAIN[19][27][20] | MAIN[19][27][21] | MAIN[19][27][23] | MAIN[19][27][22] | MAIN[19][26][22] | MAIN[19][27][24] | MAIN[19][26][24] | MAIN[19][26][26] | MAIN[19][27][27] | MAIN[19][26][28] | MAIN[19][27][29] | MAIN[19][26][30] | MAIN[19][27][31] | MAIN[19][26][18] | CELL[20].IMUX_BUFG_O[4] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[4] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[4] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][29][23] | MAIN[19][29][21] | MAIN[19][29][19] | MAIN[19][29][20] | MAIN[19][28][20] | MAIN[19][28][21] | MAIN[19][28][23] | MAIN[19][28][22] | MAIN[19][29][22] | MAIN[19][28][24] | MAIN[19][29][24] | MAIN[19][29][26] | MAIN[19][28][27] | MAIN[19][29][28] | MAIN[19][28][29] | MAIN[19][28][31] | MAIN[19][29][30] | MAIN[19][27][19] | CELL[20].IMUX_BUFG_O[5] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[5] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[5] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][33][23] | MAIN[19][33][21] | MAIN[19][33][19] | MAIN[19][33][20] | MAIN[19][32][20] | MAIN[19][32][21] | MAIN[19][32][23] | MAIN[19][32][22] | MAIN[19][33][22] | MAIN[19][32][24] | MAIN[19][33][24] | MAIN[19][33][26] | MAIN[19][32][27] | MAIN[19][33][28] | MAIN[19][32][29] | MAIN[19][32][31] | MAIN[19][33][30] | MAIN[19][31][19] | CELL[20].IMUX_BUFG_O[6] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[6] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[6] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][30][23] | MAIN[19][30][21] | MAIN[19][30][19] | MAIN[19][30][20] | MAIN[19][31][20] | MAIN[19][31][21] | MAIN[19][31][23] | MAIN[19][31][22] | MAIN[19][30][22] | MAIN[19][31][24] | MAIN[19][30][24] | MAIN[19][30][26] | MAIN[19][31][27] | MAIN[19][30][28] | MAIN[19][31][29] | MAIN[19][30][30] | MAIN[19][31][31] | MAIN[19][30][18] | CELL[20].IMUX_BUFG_O[7] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[7] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[7] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][26][39] | MAIN[19][26][37] | MAIN[19][26][35] | MAIN[19][26][36] | MAIN[19][27][36] | MAIN[19][27][37] | MAIN[19][27][39] | MAIN[19][27][38] | MAIN[19][26][38] | MAIN[19][27][40] | MAIN[19][26][40] | MAIN[19][26][42] | MAIN[19][27][43] | MAIN[19][26][44] | MAIN[19][27][45] | MAIN[19][26][46] | MAIN[19][27][47] | MAIN[19][26][34] | CELL[20].IMUX_BUFG_O[8] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][29][39] | MAIN[19][29][37] | MAIN[19][29][35] | MAIN[19][29][36] | MAIN[19][28][36] | MAIN[19][28][37] | MAIN[19][28][39] | MAIN[19][28][38] | MAIN[19][29][38] | MAIN[19][28][40] | MAIN[19][29][40] | MAIN[19][29][42] | MAIN[19][28][43] | MAIN[19][29][44] | MAIN[19][28][45] | MAIN[19][28][47] | MAIN[19][29][46] | MAIN[19][27][35] | CELL[20].IMUX_BUFG_O[9] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][33][39] | MAIN[19][33][37] | MAIN[19][33][35] | MAIN[19][33][36] | MAIN[19][32][36] | MAIN[19][32][37] | MAIN[19][32][39] | MAIN[19][32][38] | MAIN[19][33][38] | MAIN[19][32][40] | MAIN[19][33][40] | MAIN[19][33][42] | MAIN[19][32][43] | MAIN[19][33][44] | MAIN[19][32][45] | MAIN[19][32][47] | MAIN[19][33][46] | MAIN[19][31][35] | CELL[20].IMUX_BUFG_O[10] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][30][39] | MAIN[19][30][37] | MAIN[19][30][35] | MAIN[19][30][36] | MAIN[19][31][36] | MAIN[19][31][37] | MAIN[19][31][39] | MAIN[19][31][38] | MAIN[19][30][38] | MAIN[19][31][40] | MAIN[19][30][40] | MAIN[19][30][42] | MAIN[19][31][43] | MAIN[19][30][44] | MAIN[19][31][45] | MAIN[19][30][46] | MAIN[19][31][47] | MAIN[19][30][34] | CELL[20].IMUX_BUFG_O[11] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][26][55] | MAIN[19][26][53] | MAIN[19][26][51] | MAIN[19][26][52] | MAIN[19][27][52] | MAIN[19][27][53] | MAIN[19][27][55] | MAIN[19][27][54] | MAIN[19][26][54] | MAIN[19][27][56] | MAIN[19][26][56] | MAIN[19][26][58] | MAIN[19][27][59] | MAIN[19][26][60] | MAIN[19][27][61] | MAIN[19][26][62] | MAIN[19][27][63] | MAIN[19][26][50] | CELL[20].IMUX_BUFG_O[12] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][29][55] | MAIN[19][29][53] | MAIN[19][29][51] | MAIN[19][29][52] | MAIN[19][28][52] | MAIN[19][28][53] | MAIN[19][28][55] | MAIN[19][28][54] | MAIN[19][29][54] | MAIN[19][28][56] | MAIN[19][29][56] | MAIN[19][29][58] | MAIN[19][28][59] | MAIN[19][29][60] | MAIN[19][28][61] | MAIN[19][28][63] | MAIN[19][29][62] | MAIN[19][27][51] | CELL[20].IMUX_BUFG_O[13] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][33][55] | MAIN[19][33][53] | MAIN[19][33][51] | MAIN[19][33][52] | MAIN[19][32][52] | MAIN[19][32][53] | MAIN[19][32][55] | MAIN[19][32][54] | MAIN[19][33][54] | MAIN[19][32][56] | MAIN[19][33][56] | MAIN[19][33][58] | MAIN[19][32][59] | MAIN[19][33][60] | MAIN[19][32][61] | MAIN[19][32][63] | MAIN[19][33][62] | MAIN[19][31][51] | CELL[20].IMUX_BUFG_O[14] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[14] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[14] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][30][55] | MAIN[19][30][53] | MAIN[19][30][51] | MAIN[19][30][52] | MAIN[19][31][52] | MAIN[19][31][53] | MAIN[19][31][55] | MAIN[19][31][54] | MAIN[19][30][54] | MAIN[19][31][56] | MAIN[19][30][56] | MAIN[19][30][58] | MAIN[19][31][59] | MAIN[19][30][60] | MAIN[19][31][61] | MAIN[19][30][62] | MAIN[19][31][63] | MAIN[19][30][50] | CELL[20].IMUX_BUFG_O[15] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[15] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[15] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][26][7] | MAIN[20][26][5] | MAIN[20][26][3] | MAIN[20][26][4] | MAIN[20][27][4] | MAIN[20][27][5] | MAIN[20][27][7] | MAIN[20][27][6] | MAIN[20][26][6] | MAIN[20][27][8] | MAIN[20][26][8] | MAIN[20][26][10] | MAIN[20][27][11] | MAIN[20][26][12] | MAIN[20][27][13] | MAIN[20][26][14] | MAIN[20][27][15] | MAIN[20][26][2] | CELL[20].IMUX_BUFG_O[16] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][29][7] | MAIN[20][29][5] | MAIN[20][29][3] | MAIN[20][29][4] | MAIN[20][28][4] | MAIN[20][28][5] | MAIN[20][28][7] | MAIN[20][28][6] | MAIN[20][29][6] | MAIN[20][28][8] | MAIN[20][29][8] | MAIN[20][29][10] | MAIN[20][28][11] | MAIN[20][29][12] | MAIN[20][28][13] | MAIN[20][28][15] | MAIN[20][29][14] | MAIN[20][27][3] | CELL[20].IMUX_BUFG_O[17] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][33][7] | MAIN[20][33][5] | MAIN[20][33][3] | MAIN[20][33][4] | MAIN[20][32][4] | MAIN[20][32][5] | MAIN[20][32][7] | MAIN[20][32][6] | MAIN[20][33][6] | MAIN[20][32][8] | MAIN[20][33][8] | MAIN[20][33][10] | MAIN[20][32][11] | MAIN[20][33][12] | MAIN[20][32][13] | MAIN[20][32][15] | MAIN[20][33][14] | MAIN[20][31][3] | CELL[20].IMUX_BUFG_O[18] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[18] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[18] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][30][7] | MAIN[20][30][5] | MAIN[20][30][3] | MAIN[20][30][4] | MAIN[20][31][4] | MAIN[20][31][5] | MAIN[20][31][7] | MAIN[20][31][6] | MAIN[20][30][6] | MAIN[20][31][8] | MAIN[20][30][8] | MAIN[20][30][10] | MAIN[20][31][11] | MAIN[20][30][12] | MAIN[20][31][13] | MAIN[20][30][14] | MAIN[20][31][15] | MAIN[20][30][2] | CELL[20].IMUX_BUFG_O[19] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[19] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[19] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][26][23] | MAIN[20][26][21] | MAIN[20][26][19] | MAIN[20][26][20] | MAIN[20][27][20] | MAIN[20][27][21] | MAIN[20][27][23] | MAIN[20][27][22] | MAIN[20][26][22] | MAIN[20][27][24] | MAIN[20][26][24] | MAIN[20][26][26] | MAIN[20][27][27] | MAIN[20][26][28] | MAIN[20][27][29] | MAIN[20][26][30] | MAIN[20][27][31] | MAIN[20][26][18] | CELL[20].IMUX_BUFG_O[20] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[20] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[20] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][29][23] | MAIN[20][29][21] | MAIN[20][29][19] | MAIN[20][29][20] | MAIN[20][28][20] | MAIN[20][28][21] | MAIN[20][28][23] | MAIN[20][28][22] | MAIN[20][29][22] | MAIN[20][28][24] | MAIN[20][29][24] | MAIN[20][29][26] | MAIN[20][28][27] | MAIN[20][29][28] | MAIN[20][28][29] | MAIN[20][28][31] | MAIN[20][29][30] | MAIN[20][27][19] | CELL[20].IMUX_BUFG_O[21] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[21] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[21] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][33][23] | MAIN[20][33][21] | MAIN[20][33][19] | MAIN[20][33][20] | MAIN[20][32][20] | MAIN[20][32][21] | MAIN[20][32][23] | MAIN[20][32][22] | MAIN[20][33][22] | MAIN[20][32][24] | MAIN[20][33][24] | MAIN[20][33][26] | MAIN[20][32][27] | MAIN[20][33][28] | MAIN[20][32][29] | MAIN[20][32][31] | MAIN[20][33][30] | MAIN[20][31][19] | CELL[20].IMUX_BUFG_O[22] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[22] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[22] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][30][23] | MAIN[20][30][21] | MAIN[20][30][19] | MAIN[20][30][20] | MAIN[20][31][20] | MAIN[20][31][21] | MAIN[20][31][23] | MAIN[20][31][22] | MAIN[20][30][22] | MAIN[20][31][24] | MAIN[20][30][24] | MAIN[20][30][26] | MAIN[20][31][27] | MAIN[20][30][28] | MAIN[20][31][29] | MAIN[20][30][30] | MAIN[20][31][31] | MAIN[20][30][18] | CELL[20].IMUX_BUFG_O[23] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[23] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[23] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][26][39] | MAIN[20][26][37] | MAIN[20][26][35] | MAIN[20][26][36] | MAIN[20][27][36] | MAIN[20][27][37] | MAIN[20][27][39] | MAIN[20][27][38] | MAIN[20][26][38] | MAIN[20][27][40] | MAIN[20][26][40] | MAIN[20][26][42] | MAIN[20][27][43] | MAIN[20][26][44] | MAIN[20][27][45] | MAIN[20][26][46] | MAIN[20][27][47] | MAIN[20][26][34] | CELL[20].IMUX_BUFG_O[24] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][29][39] | MAIN[20][29][37] | MAIN[20][29][35] | MAIN[20][29][36] | MAIN[20][28][36] | MAIN[20][28][37] | MAIN[20][28][39] | MAIN[20][28][38] | MAIN[20][29][38] | MAIN[20][28][40] | MAIN[20][29][40] | MAIN[20][29][42] | MAIN[20][28][43] | MAIN[20][29][44] | MAIN[20][28][45] | MAIN[20][28][47] | MAIN[20][29][46] | MAIN[20][27][35] | CELL[20].IMUX_BUFG_O[25] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][33][39] | MAIN[20][33][37] | MAIN[20][33][35] | MAIN[20][33][36] | MAIN[20][32][36] | MAIN[20][32][37] | MAIN[20][32][39] | MAIN[20][32][38] | MAIN[20][33][38] | MAIN[20][32][40] | MAIN[20][33][40] | MAIN[20][33][42] | MAIN[20][32][43] | MAIN[20][33][44] | MAIN[20][32][45] | MAIN[20][32][47] | MAIN[20][33][46] | MAIN[20][31][35] | CELL[20].IMUX_BUFG_O[26] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[26] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[26] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][30][39] | MAIN[20][30][37] | MAIN[20][30][35] | MAIN[20][30][36] | MAIN[20][31][36] | MAIN[20][31][37] | MAIN[20][31][39] | MAIN[20][31][38] | MAIN[20][30][38] | MAIN[20][31][40] | MAIN[20][30][40] | MAIN[20][30][42] | MAIN[20][31][43] | MAIN[20][30][44] | MAIN[20][31][45] | MAIN[20][30][46] | MAIN[20][31][47] | MAIN[20][30][34] | CELL[20].IMUX_BUFG_O[27] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[27] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[27] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][26][55] | MAIN[20][26][53] | MAIN[20][26][51] | MAIN[20][26][52] | MAIN[20][27][52] | MAIN[20][27][53] | MAIN[20][27][55] | MAIN[20][27][54] | MAIN[20][26][54] | MAIN[20][27][56] | MAIN[20][26][56] | MAIN[20][26][58] | MAIN[20][27][59] | MAIN[20][26][60] | MAIN[20][27][61] | MAIN[20][26][62] | MAIN[20][27][63] | MAIN[20][26][50] | CELL[20].IMUX_BUFG_O[28] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[28] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[28] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][29][55] | MAIN[20][29][53] | MAIN[20][29][51] | MAIN[20][29][52] | MAIN[20][28][52] | MAIN[20][28][53] | MAIN[20][28][55] | MAIN[20][28][54] | MAIN[20][29][54] | MAIN[20][28][56] | MAIN[20][29][56] | MAIN[20][29][58] | MAIN[20][28][59] | MAIN[20][29][60] | MAIN[20][28][61] | MAIN[20][28][63] | MAIN[20][29][62] | MAIN[20][27][51] | CELL[20].IMUX_BUFG_O[29] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[29] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[29] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][33][55] | MAIN[20][33][53] | MAIN[20][33][51] | MAIN[20][33][52] | MAIN[20][32][52] | MAIN[20][32][53] | MAIN[20][32][55] | MAIN[20][32][54] | MAIN[20][33][54] | MAIN[20][32][56] | MAIN[20][33][56] | MAIN[20][33][58] | MAIN[20][32][59] | MAIN[20][33][60] | MAIN[20][32][61] | MAIN[20][32][63] | MAIN[20][33][62] | MAIN[20][31][51] | CELL[20].IMUX_BUFG_O[30] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[30] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[30] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][30][55] | MAIN[20][30][53] | MAIN[20][30][51] | MAIN[20][30][52] | MAIN[20][31][52] | MAIN[20][31][53] | MAIN[20][31][55] | MAIN[20][31][54] | MAIN[20][30][54] | MAIN[20][31][56] | MAIN[20][30][56] | MAIN[20][30][58] | MAIN[20][31][59] | MAIN[20][30][60] | MAIN[20][31][61] | MAIN[20][30][62] | MAIN[20][31][63] | MAIN[20][30][50] | CELL[20].IMUX_BUFG_O[31] |
| Source | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].IMUX_BUFG_I[31] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_TEST[31] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[6] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[8] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[5] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].OUT_PLL_N[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][28][49] | MAIN[19][28][50] | MAIN[19][29][49] | MAIN[19][28][57] | MAIN[19][29][57] | MAIN[19][28][58] | MAIN[19][29][59] | MAIN[19][28][60] | MAIN[19][29][61] | CELL[20].BUFH_TEST_W_IN |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][28][1] | MAIN[20][28][2] | MAIN[20][29][1] | MAIN[20][28][9] | MAIN[20][29][9] | MAIN[20][28][10] | MAIN[20][29][11] | MAIN[20][28][12] | MAIN[20][29][13] | CELL[20].BUFH_TEST_E_IN |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][27][24] | MAIN[18][26][24] | MAIN[18][26][26] | MAIN[18][27][27] | MAIN[18][26][28] | MAIN[18][27][29] | MAIN[18][26][30] | MAIN[18][27][31] | MAIN[18][26][23] | MAIN[18][26][21] | MAIN[18][27][23] | MAIN[18][27][22] | MAIN[18][26][22] | MAIN[18][26][19] | MAIN[18][26][20] | MAIN[18][27][20] | MAIN[18][27][21] | CELL[20].IMUX_BUFHCE_W[0] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][24] | MAIN[18][29][24] | MAIN[18][29][26] | MAIN[18][28][27] | MAIN[18][29][28] | MAIN[18][28][29] | MAIN[18][29][30] | MAIN[18][28][31] | MAIN[18][29][23] | MAIN[18][29][21] | MAIN[18][28][23] | MAIN[18][28][22] | MAIN[18][29][22] | MAIN[18][29][19] | MAIN[18][29][20] | MAIN[18][28][20] | MAIN[18][28][21] | CELL[20].IMUX_BUFHCE_W[1] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][27][40] | MAIN[18][26][40] | MAIN[18][26][42] | MAIN[18][27][43] | MAIN[18][26][44] | MAIN[18][27][45] | MAIN[18][26][46] | MAIN[18][27][47] | MAIN[18][26][39] | MAIN[18][26][37] | MAIN[18][27][39] | MAIN[18][27][38] | MAIN[18][26][38] | MAIN[18][26][35] | MAIN[18][26][36] | MAIN[18][27][36] | MAIN[18][27][37] | CELL[20].IMUX_BUFHCE_W[2] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][40] | MAIN[18][29][40] | MAIN[18][29][42] | MAIN[18][28][43] | MAIN[18][29][44] | MAIN[18][28][45] | MAIN[18][29][46] | MAIN[18][28][47] | MAIN[18][29][39] | MAIN[18][29][37] | MAIN[18][28][39] | MAIN[18][28][38] | MAIN[18][29][38] | MAIN[18][29][35] | MAIN[18][29][36] | MAIN[18][28][36] | MAIN[18][28][37] | CELL[20].IMUX_BUFHCE_W[3] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][27][56] | MAIN[18][26][56] | MAIN[18][26][58] | MAIN[18][27][59] | MAIN[18][26][60] | MAIN[18][27][61] | MAIN[18][26][62] | MAIN[18][27][63] | MAIN[18][26][55] | MAIN[18][26][53] | MAIN[18][27][55] | MAIN[18][27][54] | MAIN[18][26][54] | MAIN[18][26][51] | MAIN[18][26][52] | MAIN[18][27][52] | MAIN[18][27][53] | CELL[20].IMUX_BUFHCE_W[4] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][56] | MAIN[18][29][56] | MAIN[18][29][58] | MAIN[18][28][59] | MAIN[18][29][60] | MAIN[18][28][61] | MAIN[18][29][62] | MAIN[18][28][63] | MAIN[18][29][55] | MAIN[18][29][53] | MAIN[18][28][55] | MAIN[18][28][54] | MAIN[18][29][54] | MAIN[18][29][51] | MAIN[18][29][52] | MAIN[18][28][52] | MAIN[18][28][53] | CELL[20].IMUX_BUFHCE_W[5] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][27][8] | MAIN[21][26][8] | MAIN[21][26][10] | MAIN[21][27][11] | MAIN[21][26][12] | MAIN[21][27][13] | MAIN[21][26][14] | MAIN[21][27][15] | MAIN[21][26][7] | MAIN[21][26][5] | MAIN[21][27][7] | MAIN[21][27][6] | MAIN[21][26][6] | MAIN[21][26][3] | MAIN[21][26][4] | MAIN[21][27][4] | MAIN[21][27][5] | CELL[20].IMUX_BUFHCE_W[6] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][8] | MAIN[21][29][8] | MAIN[21][29][10] | MAIN[21][28][11] | MAIN[21][29][12] | MAIN[21][28][13] | MAIN[21][29][14] | MAIN[21][28][15] | MAIN[21][29][7] | MAIN[21][29][5] | MAIN[21][28][7] | MAIN[21][28][6] | MAIN[21][29][6] | MAIN[21][29][3] | MAIN[21][29][4] | MAIN[21][28][4] | MAIN[21][28][5] | CELL[20].IMUX_BUFHCE_W[7] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][27][24] | MAIN[21][26][24] | MAIN[21][26][26] | MAIN[21][27][27] | MAIN[21][26][28] | MAIN[21][27][29] | MAIN[21][26][30] | MAIN[21][27][31] | MAIN[21][26][23] | MAIN[21][26][21] | MAIN[21][27][23] | MAIN[21][27][22] | MAIN[21][26][22] | MAIN[21][26][19] | MAIN[21][26][20] | MAIN[21][27][20] | MAIN[21][27][21] | CELL[20].IMUX_BUFHCE_W[8] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][24] | MAIN[21][29][24] | MAIN[21][29][26] | MAIN[21][28][27] | MAIN[21][29][28] | MAIN[21][28][29] | MAIN[21][29][30] | MAIN[21][28][31] | MAIN[21][29][23] | MAIN[21][29][21] | MAIN[21][28][23] | MAIN[21][28][22] | MAIN[21][29][22] | MAIN[21][29][19] | MAIN[21][29][20] | MAIN[21][28][20] | MAIN[21][28][21] | CELL[20].IMUX_BUFHCE_W[9] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][27][40] | MAIN[21][26][40] | MAIN[21][26][42] | MAIN[21][27][43] | MAIN[21][26][44] | MAIN[21][27][45] | MAIN[21][26][46] | MAIN[21][27][47] | MAIN[21][26][39] | MAIN[21][26][37] | MAIN[21][27][39] | MAIN[21][27][38] | MAIN[21][26][38] | MAIN[21][26][35] | MAIN[21][26][36] | MAIN[21][27][36] | MAIN[21][27][37] | CELL[20].IMUX_BUFHCE_W[10] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][40] | MAIN[21][29][40] | MAIN[21][29][42] | MAIN[21][28][43] | MAIN[21][29][44] | MAIN[21][28][45] | MAIN[21][29][46] | MAIN[21][28][47] | MAIN[21][29][39] | MAIN[21][29][37] | MAIN[21][28][39] | MAIN[21][28][38] | MAIN[21][29][38] | MAIN[21][29][35] | MAIN[21][29][36] | MAIN[21][28][36] | MAIN[21][28][37] | CELL[20].IMUX_BUFHCE_W[11] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][31][24] | MAIN[18][30][24] | MAIN[18][30][26] | MAIN[18][31][27] | MAIN[18][30][28] | MAIN[18][31][29] | MAIN[18][30][30] | MAIN[18][31][31] | MAIN[18][30][23] | MAIN[18][30][21] | MAIN[18][31][23] | MAIN[18][31][22] | MAIN[18][30][22] | MAIN[18][30][19] | MAIN[18][30][20] | MAIN[18][31][20] | MAIN[18][31][21] | CELL[20].IMUX_BUFHCE_E[0] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][32][24] | MAIN[18][33][24] | MAIN[18][33][26] | MAIN[18][32][27] | MAIN[18][33][28] | MAIN[18][32][29] | MAIN[18][33][30] | MAIN[18][32][31] | MAIN[18][33][23] | MAIN[18][33][21] | MAIN[18][32][23] | MAIN[18][32][22] | MAIN[18][33][22] | MAIN[18][33][19] | MAIN[18][33][20] | MAIN[18][32][20] | MAIN[18][32][21] | CELL[20].IMUX_BUFHCE_E[1] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][31][40] | MAIN[18][30][40] | MAIN[18][30][42] | MAIN[18][31][43] | MAIN[18][30][44] | MAIN[18][31][45] | MAIN[18][30][46] | MAIN[18][31][47] | MAIN[18][30][39] | MAIN[18][30][37] | MAIN[18][31][39] | MAIN[18][31][38] | MAIN[18][30][38] | MAIN[18][30][35] | MAIN[18][30][36] | MAIN[18][31][36] | MAIN[18][31][37] | CELL[20].IMUX_BUFHCE_E[2] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][32][40] | MAIN[18][33][40] | MAIN[18][33][42] | MAIN[18][32][43] | MAIN[18][33][44] | MAIN[18][32][45] | MAIN[18][33][46] | MAIN[18][32][47] | MAIN[18][33][39] | MAIN[18][33][37] | MAIN[18][32][39] | MAIN[18][32][38] | MAIN[18][33][38] | MAIN[18][33][35] | MAIN[18][33][36] | MAIN[18][32][36] | MAIN[18][32][37] | CELL[20].IMUX_BUFHCE_E[3] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][31][56] | MAIN[18][30][56] | MAIN[18][30][58] | MAIN[18][31][59] | MAIN[18][30][60] | MAIN[18][31][61] | MAIN[18][30][62] | MAIN[18][31][63] | MAIN[18][30][55] | MAIN[18][30][53] | MAIN[18][31][55] | MAIN[18][31][54] | MAIN[18][30][54] | MAIN[18][30][51] | MAIN[18][30][52] | MAIN[18][31][52] | MAIN[18][31][53] | CELL[20].IMUX_BUFHCE_E[4] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][32][56] | MAIN[18][33][56] | MAIN[18][33][58] | MAIN[18][32][59] | MAIN[18][33][60] | MAIN[18][32][61] | MAIN[18][33][62] | MAIN[18][32][63] | MAIN[18][33][55] | MAIN[18][33][53] | MAIN[18][32][55] | MAIN[18][32][54] | MAIN[18][33][54] | MAIN[18][33][51] | MAIN[18][33][52] | MAIN[18][32][52] | MAIN[18][32][53] | CELL[20].IMUX_BUFHCE_E[5] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][31][8] | MAIN[21][30][8] | MAIN[21][30][10] | MAIN[21][31][11] | MAIN[21][30][12] | MAIN[21][31][13] | MAIN[21][30][14] | MAIN[21][31][15] | MAIN[21][30][7] | MAIN[21][30][5] | MAIN[21][31][7] | MAIN[21][31][6] | MAIN[21][30][6] | MAIN[21][30][3] | MAIN[21][30][4] | MAIN[21][31][4] | MAIN[21][31][5] | CELL[20].IMUX_BUFHCE_E[6] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][32][8] | MAIN[21][33][8] | MAIN[21][33][10] | MAIN[21][32][11] | MAIN[21][33][12] | MAIN[21][32][13] | MAIN[21][33][14] | MAIN[21][32][15] | MAIN[21][33][7] | MAIN[21][33][5] | MAIN[21][32][7] | MAIN[21][32][6] | MAIN[21][33][6] | MAIN[21][33][3] | MAIN[21][33][4] | MAIN[21][32][4] | MAIN[21][32][5] | CELL[20].IMUX_BUFHCE_E[7] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][31][24] | MAIN[21][30][24] | MAIN[21][30][26] | MAIN[21][31][27] | MAIN[21][30][28] | MAIN[21][31][29] | MAIN[21][30][30] | MAIN[21][31][31] | MAIN[21][30][23] | MAIN[21][30][21] | MAIN[21][31][23] | MAIN[21][31][22] | MAIN[21][30][22] | MAIN[21][30][19] | MAIN[21][30][20] | MAIN[21][31][20] | MAIN[21][31][21] | CELL[20].IMUX_BUFHCE_E[8] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][32][24] | MAIN[21][33][24] | MAIN[21][33][26] | MAIN[21][32][27] | MAIN[21][33][28] | MAIN[21][32][29] | MAIN[21][33][30] | MAIN[21][32][31] | MAIN[21][33][23] | MAIN[21][33][21] | MAIN[21][32][23] | MAIN[21][32][22] | MAIN[21][33][22] | MAIN[21][33][19] | MAIN[21][33][20] | MAIN[21][32][20] | MAIN[21][32][21] | CELL[20].IMUX_BUFHCE_E[9] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][31][40] | MAIN[21][30][40] | MAIN[21][30][42] | MAIN[21][31][43] | MAIN[21][30][44] | MAIN[21][31][45] | MAIN[21][30][46] | MAIN[21][31][47] | MAIN[21][30][39] | MAIN[21][30][37] | MAIN[21][31][39] | MAIN[21][31][38] | MAIN[21][30][38] | MAIN[21][30][35] | MAIN[21][30][36] | MAIN[21][31][36] | MAIN[21][31][37] | CELL[20].IMUX_BUFHCE_E[10] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][32][40] | MAIN[21][33][40] | MAIN[21][33][42] | MAIN[21][32][43] | MAIN[21][33][44] | MAIN[21][32][45] | MAIN[21][33][46] | MAIN[21][32][47] | MAIN[21][33][39] | MAIN[21][33][37] | MAIN[21][32][39] | MAIN[21][32][38] | MAIN[21][33][38] | MAIN[21][33][35] | MAIN[21][33][36] | MAIN[21][32][36] | MAIN[21][32][37] | CELL[20].IMUX_BUFHCE_E[11] |
| Source | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[8] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[16] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[24] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_E |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[9] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[17] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[25] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].BUFH_INT_E[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].BUFH_TEST_W |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[10] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[18] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[26] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[11] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[19] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[27] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[9] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[12] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[20] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[28] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[10] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[13] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[21] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[29] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[11] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[5] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[14] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[22] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[30] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[12] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GCLK_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GCLK_CMT[15] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GCLK_CMT[23] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GCLK_CMT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[13] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[3] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_S[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].OUT_PLL_N[7] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][28][1] | MAIN[19][28][2] | MAIN[19][29][1] | MAIN[19][28][9] | MAIN[19][29][9] | MAIN[19][28][10] | MAIN[19][29][11] | MAIN[19][28][12] | MAIN[19][29][13] | CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][31][1] | MAIN[19][31][2] | MAIN[19][30][1] | MAIN[19][31][9] | MAIN[19][30][9] | MAIN[19][31][10] | MAIN[19][30][11] | MAIN[19][31][12] | MAIN[19][30][13] | CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][28][17] | MAIN[19][28][18] | MAIN[19][29][17] | MAIN[19][28][25] | MAIN[19][29][25] | MAIN[19][28][26] | MAIN[19][29][27] | MAIN[19][28][28] | MAIN[19][29][29] | CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][31][17] | MAIN[19][31][18] | MAIN[19][30][17] | MAIN[19][31][25] | MAIN[19][30][25] | MAIN[19][31][26] | MAIN[19][30][27] | MAIN[19][31][28] | MAIN[19][30][29] | CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][28][33] | MAIN[19][28][34] | MAIN[19][29][33] | MAIN[19][28][41] | MAIN[19][29][41] | MAIN[19][28][42] | MAIN[19][29][43] | MAIN[19][28][44] | MAIN[19][29][45] | CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[19][31][33] | MAIN[19][31][34] | MAIN[19][30][33] | MAIN[19][31][41] | MAIN[19][30][41] | MAIN[19][31][42] | MAIN[19][30][43] | MAIN[19][31][44] | MAIN[19][30][45] | CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_W[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_W[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_W[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_W[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_W[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_W[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][31][49] | MAIN[20][31][50] | MAIN[20][30][49] | MAIN[20][31][57] | MAIN[20][30][57] | MAIN[20][31][58] | MAIN[20][30][59] | MAIN[20][31][60] | MAIN[20][30][61] | CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][28][49] | MAIN[20][28][50] | MAIN[20][29][49] | MAIN[20][28][57] | MAIN[20][29][57] | MAIN[20][28][58] | MAIN[20][29][59] | MAIN[20][28][60] | MAIN[20][29][61] | CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][31][33] | MAIN[20][31][34] | MAIN[20][30][33] | MAIN[20][31][41] | MAIN[20][30][41] | MAIN[20][31][42] | MAIN[20][30][43] | MAIN[20][31][44] | MAIN[20][30][45] | CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][28][33] | MAIN[20][28][34] | MAIN[20][29][33] | MAIN[20][28][41] | MAIN[20][29][41] | MAIN[20][28][42] | MAIN[20][29][43] | MAIN[20][28][44] | MAIN[20][29][45] | CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][31][17] | MAIN[20][31][18] | MAIN[20][30][17] | MAIN[20][31][25] | MAIN[20][30][25] | MAIN[20][31][26] | MAIN[20][30][27] | MAIN[20][31][28] | MAIN[20][30][29] | CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[20][28][17] | MAIN[20][28][18] | MAIN[20][29][17] | MAIN[20][28][25] | MAIN[20][29][25] | MAIN[20][28][26] | MAIN[20][29][27] | MAIN[20][28][28] | MAIN[20][29][29] | CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].HCLK_CMT_E[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].HCLK_CMT_E[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].HCLK_CMT_E[8] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[9] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[10] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].HCLK_CMT_E[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].RCLK_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].RCLK_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].RCLK_CMT_E[2] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[4] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].RCLK_CMT_E[5] |
| Bits | Destination |
|---|---|
| MAIN[19][30][0] | CELL[20].IMUX_PLL_CLKIN1_HCLK[0] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] |
| 1 | CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] |
| Bits | Destination |
|---|---|
| MAIN[20][30][48] | CELL[20].IMUX_PLL_CLKIN1_HCLK[1] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] |
| 1 | CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] |
| Bits | Destination |
|---|---|
| MAIN[19][30][16] | CELL[20].IMUX_PLL_CLKIN2_HCLK[0] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] |
| 1 | CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] |
| Bits | Destination |
|---|---|
| MAIN[20][30][32] | CELL[20].IMUX_PLL_CLKIN2_HCLK[1] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] |
| 1 | CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] |
| Bits | Destination |
|---|---|
| MAIN[19][30][32] | CELL[20].IMUX_PLL_CLKFB_HCLK[0] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] |
| 1 | CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] |
| Bits | Destination |
|---|---|
| MAIN[20][30][16] | CELL[20].IMUX_PLL_CLKFB_HCLK[1] |
| Source | |
| 0 | CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] |
| 1 | CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][33] | MAIN[18][28][34] | MAIN[18][29][33] | MAIN[18][28][44] | MAIN[18][29][45] | MAIN[18][28][41] | MAIN[18][29][41] | MAIN[18][28][42] | MAIN[18][29][43] | CELL[20].IMUX_PLL_CLKIN1_IO[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][17] | MAIN[21][28][18] | MAIN[21][29][17] | MAIN[21][28][28] | MAIN[21][29][29] | MAIN[21][28][25] | MAIN[21][29][25] | MAIN[21][28][26] | MAIN[21][29][27] | CELL[20].IMUX_PLL_CLKIN1_IO[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][31][33] | MAIN[18][31][34] | MAIN[18][30][33] | MAIN[18][31][44] | MAIN[18][30][45] | MAIN[18][31][41] | MAIN[18][30][41] | MAIN[18][31][42] | MAIN[18][30][43] | CELL[20].IMUX_PLL_CLKIN2_IO[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][31][17] | MAIN[21][31][18] | MAIN[21][30][17] | MAIN[21][31][28] | MAIN[21][30][29] | MAIN[21][31][25] | MAIN[21][30][25] | MAIN[21][31][26] | MAIN[21][30][27] | CELL[20].IMUX_PLL_CLKIN2_IO[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][17] | MAIN[18][28][18] | MAIN[18][29][17] | MAIN[18][28][28] | MAIN[18][29][29] | MAIN[18][28][25] | MAIN[18][29][25] | MAIN[18][28][26] | MAIN[18][29][27] | CELL[20].IMUX_PLL_CLKFB_IO[0] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][33] | MAIN[21][28][34] | MAIN[21][29][33] | MAIN[21][28][44] | MAIN[21][29][45] | MAIN[21][28][41] | MAIN[21][29][41] | MAIN[21][28][42] | MAIN[21][29][43] | CELL[20].IMUX_PLL_CLKFB_IO[1] |
| Source | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].CCIO_CMT_W[2] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].CCIO_CMT_W[3] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[4] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].CCIO_CMT_E[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].CCIO_CMT_E[3] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[0] |
| 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].CCIO_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].GIOB_CMT[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].GIOB_CMT[7] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].GIOB_CMT[0] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].GIOB_CMT[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].GIOB_CMT[3] |
| Bits | Destination | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][28][49] | MAIN[18][28][50] | MAIN[18][29][49] | MAIN[18][29][48] | MAIN[18][28][58] | MAIN[18][29][59] | MAIN[18][28][60] | MAIN[18][29][61] | MAIN[18][28][57] | MAIN[18][29][57] | CELL[20].IMUX_PLL_CLKIN1_MGT[0] |
| Source | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_E[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| Bits | Destination | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][28][1] | MAIN[21][28][2] | MAIN[21][29][1] | MAIN[21][29][0] | MAIN[21][28][10] | MAIN[21][29][11] | MAIN[21][28][12] | MAIN[21][29][13] | MAIN[21][28][9] | MAIN[21][29][9] | CELL[20].IMUX_PLL_CLKIN1_MGT[1] |
| Source | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_E[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| Bits | Destination | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[18][31][49] | MAIN[18][31][50] | MAIN[18][30][49] | MAIN[18][30][48] | MAIN[18][31][58] | MAIN[18][30][59] | MAIN[18][31][60] | MAIN[18][30][61] | MAIN[18][31][57] | MAIN[18][30][57] | CELL[20].IMUX_PLL_CLKIN2_MGT[0] |
| Source | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_E[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| Bits | Destination | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[21][31][1] | MAIN[21][31][2] | MAIN[21][30][1] | MAIN[21][30][0] | MAIN[21][31][10] | MAIN[21][30][11] | MAIN[21][31][12] | MAIN[21][30][13] | MAIN[21][31][9] | MAIN[21][30][9] | CELL[20].IMUX_PLL_CLKIN2_MGT[1] |
| Source | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[1] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[6] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[7] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[8] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[9] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_W[6] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_W[7] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_W[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[3] |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[4] |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL[20].MGT_CMT_E[4] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL[20].MGT_CMT_E[5] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL[20].MGT_CMT_E[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[2] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_E[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CELL[20].MGT_CMT_W[8] |
| Bits | Destination | |
|---|---|---|
| MAIN[17][27][62] | MAIN[17][26][62] | CELL[20].IMUX_PLL_CLKIN1[0] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKIN1_IO[0] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKIN1_HCLK[0] |
| 1 | 0 | CELL[20].IMUX_PLL_CLKIN1_MGT[0] |
| 1 | 1 | CELL[17].IMUX_CLK[0] |
| Bits | Destination | |
|---|---|---|
| MAIN[22][27][1] | MAIN[22][26][1] | CELL[20].IMUX_PLL_CLKIN1[1] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKIN1_IO[1] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKIN1_HCLK[1] |
| 1 | 0 | CELL[20].IMUX_PLL_CLKIN1_MGT[1] |
| 1 | 1 | CELL[22].IMUX_CLK[1] |
| Bits | Destination | |
|---|---|---|
| MAIN[17][27][61] | MAIN[17][26][61] | CELL[20].IMUX_PLL_CLKIN2[0] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKIN2_IO[0] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKIN2_HCLK[0] |
| 1 | 0 | CELL[20].IMUX_PLL_CLKIN2_MGT[0] |
| 1 | 1 | CELL[17].IMUX_CLK[1] |
| Bits | Destination | |
|---|---|---|
| MAIN[22][27][2] | MAIN[22][26][2] | CELL[20].IMUX_PLL_CLKIN2[1] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKIN2_IO[1] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKIN2_HCLK[1] |
| 1 | 0 | CELL[20].IMUX_PLL_CLKIN2_MGT[1] |
| 1 | 1 | CELL[22].IMUX_CLK[0] |
| Bits | Destination | |
|---|---|---|
| MAIN[17][27][63] | MAIN[17][26][63] | CELL[20].IMUX_PLL_CLKFB[0] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKFB_IO[0] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKFB_HCLK[0] |
| 1 | 1 | CELL[18].IMUX_CLK[1] |
| Bits | Destination | |
|---|---|---|
| MAIN[22][27][0] | MAIN[22][26][0] | CELL[20].IMUX_PLL_CLKFB[1] |
| Source | ||
| 0 | 0 | CELL[20].IMUX_PLL_CLKFB_IO[1] |
| 0 | 1 | CELL[20].IMUX_PLL_CLKFB_HCLK[1] |
| 1 | 1 | CELL[21].IMUX_CLK[0] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[17][26][22] | MAIN[17][27][23] | MAIN[17][26][23] | CELL[20].OMUX_PLL_CASC[0] |
| Source | |||
| 0 | 0 | 0 | CELL[20].OUT_PLL_S[0] |
| 0 | 0 | 1 | CELL[20].OUT_PLL_S[2] |
| 0 | 1 | 0 | CELL[20].OUT_PLL_S[4] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_S[6] |
| 1 | 0 | 0 | CELL[20].OUT_PLL_S[8] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_S[9] |
| 1 | 1 | 0 | CELL[20].OUT_PLL_S[10] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_S[11] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[22][26][41] | MAIN[22][27][40] | MAIN[22][26][40] | CELL[20].OMUX_PLL_CASC[1] |
| Source | |||
| 0 | 0 | 0 | CELL[20].OUT_PLL_N[0] |
| 0 | 0 | 1 | CELL[20].OUT_PLL_N[2] |
| 0 | 1 | 0 | CELL[20].OUT_PLL_N[4] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_N[6] |
| 1 | 0 | 0 | CELL[20].OUT_PLL_N[8] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_N[9] |
| 1 | 1 | 0 | CELL[20].OUT_PLL_N[10] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_N[11] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[17][27][31] | MAIN[17][26][31] | MAIN[17][26][33] | CELL[20].OMUX_PLL_PERF_S[0] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_S[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_S[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_S[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[17][27][30] | MAIN[17][26][30] | MAIN[17][27][33] | CELL[20].OMUX_PLL_PERF_S[1] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_S[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_S[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_S[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[17][27][29] | MAIN[17][26][29] | MAIN[17][26][32] | CELL[20].OMUX_PLL_PERF_S[2] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_S[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_S[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_S[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[17][27][28] | MAIN[17][26][28] | MAIN[17][27][32] | CELL[20].OMUX_PLL_PERF_S[3] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_S[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_S[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_S[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_S[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[22][27][32] | MAIN[22][26][32] | MAIN[22][26][30] | CELL[20].OMUX_PLL_PERF_N[0] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_N[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_N[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_N[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[22][27][33] | MAIN[22][26][33] | MAIN[22][27][30] | CELL[20].OMUX_PLL_PERF_N[1] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_N[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_N[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_N[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[22][27][34] | MAIN[22][26][34] | MAIN[22][26][31] | CELL[20].OMUX_PLL_PERF_N[2] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_N[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_N[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_N[6] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[22][27][35] | MAIN[22][26][35] | MAIN[22][27][31] | CELL[20].OMUX_PLL_PERF_N[3] |
| Source | |||
| 0 | 0 | 0 | off |
| 0 | 0 | 1 | CELL[20].OUT_PLL_N[0] |
| 0 | 1 | 1 | CELL[20].OUT_PLL_N[2] |
| 1 | 0 | 1 | CELL[20].OUT_PLL_N[4] |
| 1 | 1 | 1 | CELL[20].OUT_PLL_N[6] |
Bels PLL_V6
| Pin | Direction | PLL[0] | PLL[1] |
|---|---|---|---|
| CLKIN1 | in | CELL[20].IMUX_PLL_CLKIN1[0] | CELL[20].IMUX_PLL_CLKIN1[1] |
| CLKIN2 | in | CELL[20].IMUX_PLL_CLKIN2[0] | CELL[20].IMUX_PLL_CLKIN2[1] |
| CLKINSEL | in | CELL[3].IMUX_IMUX[11] invert by MAIN[3][26][45] | CELL[36].IMUX_IMUX[36] invert by MAIN[36][26][18] |
| CLKFBIN | in | CELL[20].IMUX_PLL_CLKFB[0] | CELL[20].IMUX_PLL_CLKFB[1] |
| CLKIN_CASC | in | CELL[20].OMUX_PLL_CASC[1] | CELL[20].OMUX_PLL_CASC[0] |
| CLKFB_CASC | in | CELL[20].OMUX_PLL_CASC[0] | CELL[20].OMUX_PLL_CASC[1] |
| RST | in | CELL[3].IMUX_IMUX[8] invert by MAIN[3][26][47] | CELL[36].IMUX_IMUX[39] invert by MAIN[36][26][16] |
| PWRDWN | in | CELL[3].IMUX_IMUX[34] invert by MAIN[3][27][47] | CELL[36].IMUX_IMUX[13] invert by MAIN[36][27][16] |
| DCLK | in | CELL[2].IMUX_CLK[0] | CELL[37].IMUX_CLK[1] |
| DEN | in | CELL[3].IMUX_IMUX[9] | CELL[36].IMUX_IMUX[38] |
| DWE | in | CELL[3].IMUX_IMUX[10] | CELL[36].IMUX_IMUX[37] |
| DADDR[0] | in | CELL[5].IMUX_IMUX[7] | CELL[34].IMUX_IMUX[40] |
| DADDR[1] | in | CELL[5].IMUX_IMUX[6] | CELL[34].IMUX_IMUX[41] |
| DADDR[2] | in | CELL[5].IMUX_IMUX[5] | CELL[34].IMUX_IMUX[42] |
| DADDR[3] | in | CELL[5].IMUX_IMUX[43] | CELL[34].IMUX_IMUX[4] |
| DADDR[4] | in | CELL[5].IMUX_IMUX[42] | CELL[34].IMUX_IMUX[5] |
| DADDR[5] | in | CELL[5].IMUX_IMUX[41] | CELL[34].IMUX_IMUX[6] |
| DADDR[6] | in | CELL[5].IMUX_IMUX[40] | CELL[34].IMUX_IMUX[7] |
| DI[0] | in | CELL[4].IMUX_IMUX[15] | CELL[35].IMUX_IMUX[32] |
| DI[1] | in | CELL[4].IMUX_IMUX[14] | CELL[35].IMUX_IMUX[33] |
| DI[2] | in | CELL[4].IMUX_IMUX[13] | CELL[35].IMUX_IMUX[34] |
| DI[3] | in | CELL[4].IMUX_IMUX[12] | CELL[35].IMUX_IMUX[35] |
| DI[4] | in | CELL[4].IMUX_IMUX[11] | CELL[35].IMUX_IMUX[36] |
| DI[5] | in | CELL[4].IMUX_IMUX[10] | CELL[35].IMUX_IMUX[37] |
| DI[6] | in | CELL[4].IMUX_IMUX[17] | CELL[35].IMUX_IMUX[30] |
| DI[7] | in | CELL[4].IMUX_IMUX[16] | CELL[35].IMUX_IMUX[31] |
| DI[8] | in | CELL[3].IMUX_IMUX[39] | CELL[36].IMUX_IMUX[8] |
| DI[9] | in | CELL[3].IMUX_IMUX[7] | CELL[36].IMUX_IMUX[40] |
| DI[10] | in | CELL[3].IMUX_IMUX[22] | CELL[36].IMUX_IMUX[25] |
| DI[11] | in | CELL[3].IMUX_IMUX[37] | CELL[36].IMUX_IMUX[10] |
| DI[12] | in | CELL[3].IMUX_IMUX[13] | CELL[36].IMUX_IMUX[34] |
| DI[13] | in | CELL[3].IMUX_IMUX[36] | CELL[36].IMUX_IMUX[11] |
| DI[14] | in | CELL[3].IMUX_IMUX[12] | CELL[36].IMUX_IMUX[35] |
| DI[15] | in | CELL[3].IMUX_IMUX[35] | CELL[36].IMUX_IMUX[12] |
| PSCLK | in | CELL[2].IMUX_CLK[1] | CELL[37].IMUX_CLK[0] |
| PSEN | in | CELL[3].IMUX_IMUX[33] invert by MAIN[3][27][46] | CELL[36].IMUX_IMUX[14] invert by MAIN[36][27][17] |
| PSINCDEC | in | CELL[3].IMUX_IMUX[32] invert by MAIN[3][26][46] | CELL[36].IMUX_IMUX[15] invert by MAIN[36][26][17] |
| TESTIN[0] | in | CELL[17].IMUX_IMUX[14] | CELL[22].IMUX_IMUX[33] |
| TESTIN[1] | in | CELL[8].IMUX_IMUX[27] | CELL[31].IMUX_IMUX[20] |
| TESTIN[2] | in | CELL[8].IMUX_IMUX[11] | CELL[31].IMUX_IMUX[36] |
| TESTIN[3] | in | CELL[8].IMUX_IMUX[26] | CELL[31].IMUX_IMUX[21] |
| TESTIN[4] | in | CELL[8].IMUX_IMUX[10] | CELL[31].IMUX_IMUX[37] |
| TESTIN[5] | in | CELL[8].IMUX_IMUX[25] | CELL[31].IMUX_IMUX[22] |
| TESTIN[6] | in | CELL[8].IMUX_IMUX[9] | CELL[31].IMUX_IMUX[38] |
| TESTIN[7] | in | CELL[8].IMUX_IMUX[24] | CELL[31].IMUX_IMUX[23] |
| TESTIN[8] | in | CELL[8].IMUX_IMUX[8] | CELL[31].IMUX_IMUX[39] |
| TESTIN[9] | in | CELL[7].IMUX_IMUX[39] | CELL[32].IMUX_IMUX[8] |
| TESTIN[10] | in | CELL[7].IMUX_IMUX[23] | CELL[32].IMUX_IMUX[24] |
| TESTIN[11] | in | CELL[7].IMUX_IMUX[7] | CELL[32].IMUX_IMUX[40] |
| TESTIN[12] | in | CELL[7].IMUX_IMUX[38] | CELL[32].IMUX_IMUX[9] |
| TESTIN[13] | in | CELL[7].IMUX_IMUX[22] | CELL[32].IMUX_IMUX[25] |
| TESTIN[14] | in | CELL[7].IMUX_IMUX[6] | CELL[32].IMUX_IMUX[41] |
| TESTIN[15] | in | CELL[7].IMUX_IMUX[37] | CELL[32].IMUX_IMUX[10] |
| TESTIN[16] | in | CELL[7].IMUX_IMUX[21] | CELL[32].IMUX_IMUX[26] |
| TESTIN[17] | in | CELL[7].IMUX_IMUX[5] | CELL[32].IMUX_IMUX[42] |
| TESTIN[18] | in | CELL[7].IMUX_IMUX[28] | CELL[32].IMUX_IMUX[19] |
| TESTIN[19] | in | CELL[7].IMUX_IMUX[12] | CELL[32].IMUX_IMUX[35] |
| TESTIN[20] | in | CELL[7].IMUX_IMUX[43] | CELL[32].IMUX_IMUX[4] |
| TESTIN[21] | in | CELL[7].IMUX_IMUX[27] | CELL[32].IMUX_IMUX[20] |
| TESTIN[22] | in | CELL[7].IMUX_IMUX[11] | CELL[32].IMUX_IMUX[36] |
| TESTIN[23] | in | CELL[7].IMUX_IMUX[42] | CELL[32].IMUX_IMUX[5] |
| TESTIN[24] | in | CELL[7].IMUX_IMUX[26] | CELL[32].IMUX_IMUX[21] |
| TESTIN[25] | in | CELL[7].IMUX_IMUX[10] | CELL[32].IMUX_IMUX[37] |
| TESTIN[26] | in | CELL[7].IMUX_IMUX[41] | CELL[32].IMUX_IMUX[6] |
| TESTIN[27] | in | CELL[7].IMUX_IMUX[25] | CELL[32].IMUX_IMUX[22] |
| TESTIN[28] | in | CELL[7].IMUX_IMUX[9] | CELL[32].IMUX_IMUX[38] |
| TESTIN[29] | in | CELL[7].IMUX_IMUX[40] | CELL[32].IMUX_IMUX[7] |
| TESTIN[30] | in | CELL[7].IMUX_IMUX[24] | CELL[32].IMUX_IMUX[23] |
| TESTIN[31] | in | CELL[7].IMUX_IMUX[8] | CELL[32].IMUX_IMUX[39] |
| CLKOUT0 | out | CELL[20].OUT_PLL_S[0] | CELL[20].OUT_PLL_N[0] |
| CLKOUT0B | out | CELL[20].OUT_PLL_S[1] | CELL[20].OUT_PLL_N[1] |
| CLKOUT1 | out | CELL[20].OUT_PLL_S[2] | CELL[20].OUT_PLL_N[2] |
| CLKOUT1B | out | CELL[20].OUT_PLL_S[3] | CELL[20].OUT_PLL_N[3] |
| CLKOUT2 | out | CELL[20].OUT_PLL_S[4] | CELL[20].OUT_PLL_N[4] |
| CLKOUT2B | out | CELL[20].OUT_PLL_S[5] | CELL[20].OUT_PLL_N[5] |
| CLKOUT3 | out | CELL[20].OUT_PLL_S[6] | CELL[20].OUT_PLL_N[6] |
| CLKOUT3B | out | CELL[20].OUT_PLL_S[7] | CELL[20].OUT_PLL_N[7] |
| CLKOUT4 | out | CELL[20].OUT_PLL_S[8] | CELL[20].OUT_PLL_N[8] |
| CLKOUT5 | out | CELL[20].OUT_PLL_S[9] | CELL[20].OUT_PLL_N[9] |
| CLKOUT6 | out | CELL[20].OUT_PLL_S[10] | CELL[20].OUT_PLL_N[10] |
| CLKFBOUT | out | CELL[20].OUT_PLL_S[11] | CELL[20].OUT_PLL_N[11] |
| CLKFBOUTB | out | CELL[20].OUT_PLL_S[12] | CELL[20].OUT_PLL_N[12] |
| TMUXOUT | out | CELL[20].OUT_PLL_S[13] | CELL[20].OUT_PLL_N[13] |
| LOCKED | out | CELL[2].OUT_BEL[8] | CELL[37].OUT_BEL[17] |
| DRDY | out | CELL[2].OUT_BEL[18] | CELL[37].OUT_BEL[11] |
| DO[0] | out | CELL[3].OUT_BEL[7] | CELL[36].OUT_BEL[4] |
| DO[1] | out | CELL[3].OUT_BEL[3] | CELL[36].OUT_BEL[0] |
| DO[2] | out | CELL[3].OUT_BEL[2] | CELL[36].OUT_BEL[1] |
| DO[3] | out | CELL[3].OUT_BEL[6] | CELL[36].OUT_BEL[5] |
| DO[4] | out | CELL[3].OUT_BEL[5] | CELL[36].OUT_BEL[6] |
| DO[5] | out | CELL[3].OUT_BEL[1] | CELL[36].OUT_BEL[2] |
| DO[6] | out | CELL[3].OUT_BEL[0] | CELL[36].OUT_BEL[3] |
| DO[7] | out | CELL[3].OUT_BEL[4] | CELL[36].OUT_BEL[7] |
| DO[8] | out | CELL[2].OUT_BEL[17] | CELL[37].OUT_BEL[8] |
| DO[9] | out | CELL[2].OUT_BEL[11] | CELL[37].OUT_BEL[18] |
| DO[10] | out | CELL[2].OUT_BEL[15] | CELL[37].OUT_BEL[22] |
| DO[11] | out | CELL[2].OUT_BEL[2] | CELL[37].OUT_BEL[1] |
| DO[12] | out | CELL[2].OUT_BEL[16] | CELL[37].OUT_BEL[9] |
| DO[13] | out | CELL[2].OUT_BEL[19] | CELL[37].OUT_BEL[10] |
| DO[14] | out | CELL[2].OUT_BEL[9] | CELL[37].OUT_BEL[16] |
| DO[15] | out | CELL[2].OUT_BEL[1] | CELL[37].OUT_BEL[2] |
| PSDONE | out | CELL[2].OUT_BEL[0] | CELL[37].OUT_BEL[3] |
| CLKINSTOPPED | out | CELL[4].OUT_BEL[4] | CELL[35].OUT_BEL[7] |
| CLKFBSTOPPED | out | CELL[4].OUT_BEL[0] | CELL[35].OUT_BEL[3] |
| TESTOUT[0] | out | CELL[8].OUT_BEL[0] | CELL[31].OUT_BEL[3] |
| TESTOUT[1] | out | CELL[8].OUT_BEL[4] | CELL[31].OUT_BEL[7] |
| TESTOUT[2] | out | CELL[7].OUT_BEL[7] | CELL[32].OUT_BEL[4] |
| TESTOUT[3] | out | CELL[7].OUT_BEL[3] | CELL[32].OUT_BEL[0] |
| TESTOUT[4] | out | CELL[7].OUT_BEL[2] | CELL[32].OUT_BEL[1] |
| TESTOUT[5] | out | CELL[7].OUT_BEL[6] | CELL[32].OUT_BEL[5] |
| TESTOUT[6] | out | CELL[7].OUT_BEL[5] | CELL[32].OUT_BEL[6] |
| TESTOUT[7] | out | CELL[7].OUT_BEL[1] | CELL[32].OUT_BEL[2] |
| TESTOUT[8] | out | CELL[7].OUT_BEL[0] | CELL[32].OUT_BEL[3] |
| TESTOUT[9] | out | CELL[7].OUT_BEL[4] | CELL[32].OUT_BEL[7] |
| TESTOUT[10] | out | CELL[6].OUT_BEL[7] | CELL[33].OUT_BEL[4] |
| TESTOUT[11] | out | CELL[6].OUT_BEL[3] | CELL[33].OUT_BEL[0] |
| TESTOUT[12] | out | CELL[6].OUT_BEL[2] | CELL[33].OUT_BEL[1] |
| TESTOUT[13] | out | CELL[6].OUT_BEL[6] | CELL[33].OUT_BEL[5] |
| TESTOUT[14] | out | CELL[6].OUT_BEL[5] | CELL[33].OUT_BEL[6] |
| TESTOUT[15] | out | CELL[6].OUT_BEL[1] | CELL[33].OUT_BEL[2] |
| TESTOUT[16] | out | CELL[6].OUT_BEL[0] | CELL[33].OUT_BEL[3] |
| TESTOUT[17] | out | CELL[6].OUT_BEL[4] | CELL[33].OUT_BEL[7] |
| TESTOUT[18] | out | CELL[5].OUT_BEL[7] | CELL[34].OUT_BEL[4] |
| TESTOUT[19] | out | CELL[5].OUT_BEL[3] | CELL[34].OUT_BEL[0] |
| TESTOUT[20] | out | CELL[5].OUT_BEL[2] | CELL[34].OUT_BEL[1] |
| TESTOUT[21] | out | CELL[5].OUT_BEL[6] | CELL[34].OUT_BEL[5] |
| TESTOUT[22] | out | CELL[5].OUT_BEL[5] | CELL[34].OUT_BEL[6] |
| TESTOUT[23] | out | CELL[5].OUT_BEL[1] | CELL[34].OUT_BEL[2] |
| TESTOUT[24] | out | CELL[5].OUT_BEL[0] | CELL[34].OUT_BEL[3] |
| TESTOUT[25] | out | CELL[5].OUT_BEL[4] | CELL[34].OUT_BEL[7] |
| TESTOUT[26] | out | CELL[4].OUT_BEL[7] | CELL[35].OUT_BEL[4] |
| TESTOUT[27] | out | CELL[4].OUT_BEL[3] | CELL[35].OUT_BEL[0] |
| TESTOUT[28] | out | CELL[4].OUT_BEL[2] | CELL[35].OUT_BEL[1] |
| TESTOUT[29] | out | CELL[4].OUT_BEL[6] | CELL[35].OUT_BEL[5] |
| TESTOUT[30] | out | CELL[4].OUT_BEL[5] | CELL[35].OUT_BEL[6] |
| TESTOUT[31] | out | CELL[4].OUT_BEL[1] | CELL[35].OUT_BEL[2] |
| TESTOUT[32] | out | CELL[17].IMUX_SPEC[3] | CELL[27].OUT_BEL[3] |
| TESTOUT[33] | out | CELL[17].IMUX_SPEC[3] | CELL[27].OUT_BEL[7] |
| TESTOUT[34] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[35] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[36] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[37] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[38] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[39] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[40] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[41] | out | CELL[17].IMUX_SPEC[3] | CELL[37].IMUX_SPEC[3] |
| TESTOUT[42] | out | CELL[10].OUT_BEL[7] | CELL[29].OUT_BEL[4] |
| TESTOUT[43] | out | CELL[10].OUT_BEL[3] | CELL[29].OUT_BEL[0] |
| TESTOUT[44] | out | CELL[10].OUT_BEL[2] | CELL[29].OUT_BEL[1] |
| TESTOUT[45] | out | CELL[10].OUT_BEL[6] | CELL[29].OUT_BEL[5] |
| TESTOUT[46] | out | CELL[10].OUT_BEL[5] | CELL[29].OUT_BEL[6] |
| TESTOUT[47] | out | CELL[10].OUT_BEL[1] | CELL[29].OUT_BEL[2] |
| TESTOUT[48] | out | CELL[10].OUT_BEL[0] | CELL[29].OUT_BEL[3] |
| TESTOUT[49] | out | CELL[10].OUT_BEL[4] | CELL[29].OUT_BEL[7] |
| TESTOUT[50] | out | CELL[9].OUT_BEL[7] | CELL[30].OUT_BEL[4] |
| TESTOUT[51] | out | CELL[9].OUT_BEL[3] | CELL[30].OUT_BEL[0] |
| TESTOUT[52] | out | CELL[9].OUT_BEL[2] | CELL[30].OUT_BEL[1] |
| TESTOUT[53] | out | CELL[9].OUT_BEL[6] | CELL[30].OUT_BEL[5] |
| TESTOUT[54] | out | CELL[9].OUT_BEL[5] | CELL[30].OUT_BEL[6] |
| TESTOUT[55] | out | CELL[9].OUT_BEL[1] | CELL[30].OUT_BEL[2] |
| TESTOUT[56] | out | CELL[9].OUT_BEL[0] | CELL[30].OUT_BEL[3] |
| TESTOUT[57] | out | CELL[9].OUT_BEL[4] | CELL[30].OUT_BEL[7] |
| TESTOUT[58] | out | CELL[8].OUT_BEL[7] | CELL[31].OUT_BEL[4] |
| TESTOUT[59] | out | CELL[8].OUT_BEL[3] | CELL[31].OUT_BEL[0] |
| TESTOUT[60] | out | CELL[8].OUT_BEL[2] | CELL[31].OUT_BEL[1] |
| TESTOUT[61] | out | CELL[8].OUT_BEL[6] | CELL[31].OUT_BEL[5] |
| TESTOUT[62] | out | CELL[8].OUT_BEL[5] | CELL[31].OUT_BEL[6] |
| TESTOUT[63] | out | CELL[8].OUT_BEL[1] | CELL[31].OUT_BEL[2] |
Bels PPR_FRAME
| Pin | Direction | PPR_FRAME |
|---|---|---|
| CLK | in | CELL[39].IMUX_CLK[1] |
| CTLB | in | CELL[35].IMUX_IMUX[43] |
| ENB | in | CELL[35].IMUX_IMUX[42] |
| SHIFTB | in | CELL[35].IMUX_IMUX[40] |
| UPDATEB | in | CELL[35].IMUX_IMUX[41] |
| DA[0] | in | CELL[20].IMUX_IMUX[44] |
| DA[1] | in | CELL[20].IMUX_IMUX[45] |
| DA[2] | in | CELL[20].IMUX_IMUX[46] |
| DA[3] | in | CELL[20].IMUX_IMUX[47] |
| DA[4] | in | CELL[21].IMUX_IMUX[44] |
| DA[5] | in | CELL[21].IMUX_IMUX[45] |
| DA[6] | in | CELL[21].IMUX_IMUX[46] |
| DA[7] | in | CELL[21].IMUX_IMUX[47] |
| DA[8] | in | CELL[22].IMUX_IMUX[44] |
| DA[9] | in | CELL[22].IMUX_IMUX[45] |
| DA[10] | in | CELL[22].IMUX_IMUX[46] |
| DA[11] | in | CELL[22].IMUX_IMUX[47] |
| DA[12] | in | CELL[23].IMUX_IMUX[44] |
| DA[13] | in | CELL[23].IMUX_IMUX[45] |
| DA[14] | in | CELL[23].IMUX_IMUX[46] |
| DA[15] | in | CELL[23].IMUX_IMUX[47] |
| DA[16] | in | CELL[24].IMUX_IMUX[44] |
| DA[17] | in | CELL[24].IMUX_IMUX[45] |
| DA[18] | in | CELL[24].IMUX_IMUX[46] |
| DA[19] | in | CELL[24].IMUX_IMUX[47] |
| DA[20] | in | CELL[25].IMUX_IMUX[44] |
| DA[21] | in | CELL[25].IMUX_IMUX[45] |
| DA[22] | in | CELL[25].IMUX_IMUX[46] |
| DA[23] | in | CELL[25].IMUX_IMUX[47] |
| DA[24] | in | CELL[26].IMUX_IMUX[44] |
| DA[25] | in | CELL[26].IMUX_IMUX[45] |
| DA[26] | in | CELL[26].IMUX_IMUX[46] |
| DA[27] | in | CELL[26].IMUX_IMUX[47] |
| DA[28] | in | CELL[27].IMUX_IMUX[44] |
| DA[29] | in | CELL[27].IMUX_IMUX[45] |
| DA[30] | in | CELL[27].IMUX_IMUX[46] |
| DA[31] | in | CELL[27].IMUX_IMUX[47] |
| DA[32] | in | CELL[28].IMUX_IMUX[44] |
| DA[33] | in | CELL[28].IMUX_IMUX[45] |
| DA[34] | in | CELL[28].IMUX_IMUX[46] |
| DA[35] | in | CELL[28].IMUX_IMUX[47] |
| DA[36] | in | CELL[29].IMUX_IMUX[44] |
| DA[37] | in | CELL[29].IMUX_IMUX[45] |
| DA[38] | in | CELL[29].IMUX_IMUX[46] |
| DA[39] | in | CELL[29].IMUX_IMUX[47] |
| DA[40] | in | CELL[30].IMUX_IMUX[44] |
| DA[41] | in | CELL[30].IMUX_IMUX[45] |
| DA[42] | in | CELL[30].IMUX_IMUX[46] |
| DA[43] | in | CELL[30].IMUX_IMUX[47] |
| DA[44] | in | CELL[31].IMUX_IMUX[44] |
| DA[45] | in | CELL[31].IMUX_IMUX[45] |
| DA[46] | in | CELL[31].IMUX_IMUX[46] |
| DA[47] | in | CELL[31].IMUX_IMUX[47] |
| DA[48] | in | CELL[32].IMUX_IMUX[44] |
| DA[49] | in | CELL[32].IMUX_IMUX[45] |
| DA[50] | in | CELL[32].IMUX_IMUX[46] |
| DA[51] | in | CELL[32].IMUX_IMUX[47] |
| DA[52] | in | CELL[33].IMUX_IMUX[44] |
| DA[53] | in | CELL[33].IMUX_IMUX[45] |
| DA[54] | in | CELL[33].IMUX_IMUX[46] |
| DA[55] | in | CELL[33].IMUX_IMUX[47] |
| DA[56] | in | CELL[34].IMUX_IMUX[44] |
| DA[57] | in | CELL[34].IMUX_IMUX[45] |
| DA[58] | in | CELL[34].IMUX_IMUX[46] |
| DA[59] | in | CELL[34].IMUX_IMUX[47] |
| DA[60] | in | CELL[35].IMUX_IMUX[44] |
| DA[61] | in | CELL[35].IMUX_IMUX[45] |
| DA[62] | in | CELL[35].IMUX_IMUX[46] |
| DA[63] | in | CELL[35].IMUX_IMUX[47] |
| DA[64] | in | CELL[36].IMUX_IMUX[44] |
| DA[65] | in | CELL[36].IMUX_IMUX[45] |
| DA[66] | in | CELL[36].IMUX_IMUX[46] |
| DA[67] | in | CELL[36].IMUX_IMUX[47] |
| DA[68] | in | CELL[37].IMUX_IMUX[44] |
| DA[69] | in | CELL[37].IMUX_IMUX[45] |
| DA[70] | in | CELL[37].IMUX_IMUX[46] |
| DA[71] | in | CELL[37].IMUX_IMUX[47] |
| DA[72] | in | CELL[38].IMUX_IMUX[44] |
| DA[73] | in | CELL[38].IMUX_IMUX[45] |
| DA[74] | in | CELL[38].IMUX_IMUX[46] |
| DA[75] | in | CELL[38].IMUX_IMUX[47] |
| DA[76] | in | CELL[39].IMUX_IMUX[44] |
| DA[77] | in | CELL[39].IMUX_IMUX[45] |
| DA[78] | in | CELL[39].IMUX_IMUX[46] |
| DA[79] | in | CELL[39].IMUX_IMUX[47] |
| DB[0] | in | CELL[0].IMUX_IMUX[44] |
| DB[1] | in | CELL[0].IMUX_IMUX[45] |
| DB[2] | in | CELL[0].IMUX_IMUX[46] |
| DB[3] | in | CELL[0].IMUX_IMUX[47] |
| DB[4] | in | CELL[1].IMUX_IMUX[44] |
| DB[5] | in | CELL[1].IMUX_IMUX[45] |
| DB[6] | in | CELL[1].IMUX_IMUX[46] |
| DB[7] | in | CELL[1].IMUX_IMUX[47] |
| DB[8] | in | CELL[2].IMUX_IMUX[44] |
| DB[9] | in | CELL[2].IMUX_IMUX[45] |
| DB[10] | in | CELL[2].IMUX_IMUX[46] |
| DB[11] | in | CELL[2].IMUX_IMUX[47] |
| DB[12] | in | CELL[3].IMUX_IMUX[44] |
| DB[13] | in | CELL[3].IMUX_IMUX[45] |
| DB[14] | in | CELL[3].IMUX_IMUX[46] |
| DB[15] | in | CELL[3].IMUX_IMUX[47] |
| DB[16] | in | CELL[4].IMUX_IMUX[44] |
| DB[17] | in | CELL[4].IMUX_IMUX[45] |
| DB[18] | in | CELL[4].IMUX_IMUX[46] |
| DB[19] | in | CELL[4].IMUX_IMUX[47] |
| DB[20] | in | CELL[5].IMUX_IMUX[44] |
| DB[21] | in | CELL[5].IMUX_IMUX[45] |
| DB[22] | in | CELL[5].IMUX_IMUX[46] |
| DB[23] | in | CELL[5].IMUX_IMUX[47] |
| DB[24] | in | CELL[6].IMUX_IMUX[44] |
| DB[25] | in | CELL[6].IMUX_IMUX[45] |
| DB[26] | in | CELL[6].IMUX_IMUX[46] |
| DB[27] | in | CELL[6].IMUX_IMUX[47] |
| DB[28] | in | CELL[7].IMUX_IMUX[44] |
| DB[29] | in | CELL[7].IMUX_IMUX[45] |
| DB[30] | in | CELL[7].IMUX_IMUX[46] |
| DB[31] | in | CELL[7].IMUX_IMUX[47] |
| DB[32] | in | CELL[8].IMUX_IMUX[44] |
| DB[33] | in | CELL[8].IMUX_IMUX[45] |
| DB[34] | in | CELL[8].IMUX_IMUX[46] |
| DB[35] | in | CELL[8].IMUX_IMUX[47] |
| DB[36] | in | CELL[9].IMUX_IMUX[44] |
| DB[37] | in | CELL[9].IMUX_IMUX[45] |
| DB[38] | in | CELL[9].IMUX_IMUX[46] |
| DB[39] | in | CELL[9].IMUX_IMUX[47] |
| DB[40] | in | CELL[10].IMUX_IMUX[44] |
| DB[41] | in | CELL[10].IMUX_IMUX[45] |
| DB[42] | in | CELL[10].IMUX_IMUX[46] |
| DB[43] | in | CELL[10].IMUX_IMUX[47] |
| DB[44] | in | CELL[11].IMUX_IMUX[44] |
| DB[45] | in | CELL[11].IMUX_IMUX[45] |
| DB[46] | in | CELL[11].IMUX_IMUX[46] |
| DB[47] | in | CELL[11].IMUX_IMUX[47] |
| DB[48] | in | CELL[12].IMUX_IMUX[44] |
| DB[49] | in | CELL[12].IMUX_IMUX[45] |
| DB[50] | in | CELL[12].IMUX_IMUX[46] |
| DB[51] | in | CELL[12].IMUX_IMUX[47] |
| DB[52] | in | CELL[13].IMUX_IMUX[44] |
| DB[53] | in | CELL[13].IMUX_IMUX[45] |
| DB[54] | in | CELL[13].IMUX_IMUX[46] |
| DB[55] | in | CELL[13].IMUX_IMUX[47] |
| DB[56] | in | CELL[14].IMUX_IMUX[44] |
| DB[57] | in | CELL[14].IMUX_IMUX[45] |
| DB[58] | in | CELL[14].IMUX_IMUX[46] |
| DB[59] | in | CELL[14].IMUX_IMUX[47] |
| DB[60] | in | CELL[15].IMUX_IMUX[44] |
| DB[61] | in | CELL[15].IMUX_IMUX[45] |
| DB[62] | in | CELL[15].IMUX_IMUX[46] |
| DB[63] | in | CELL[15].IMUX_IMUX[47] |
| DB[64] | in | CELL[16].IMUX_IMUX[44] |
| DB[65] | in | CELL[16].IMUX_IMUX[45] |
| DB[66] | in | CELL[16].IMUX_IMUX[46] |
| DB[67] | in | CELL[16].IMUX_IMUX[47] |
| DB[68] | in | CELL[17].IMUX_IMUX[44] |
| DB[69] | in | CELL[17].IMUX_IMUX[45] |
| DB[70] | in | CELL[17].IMUX_IMUX[46] |
| DB[71] | in | CELL[17].IMUX_IMUX[47] |
| DB[72] | in | CELL[18].IMUX_IMUX[44] |
| DB[73] | in | CELL[18].IMUX_IMUX[45] |
| DB[74] | in | CELL[18].IMUX_IMUX[46] |
| DB[75] | in | CELL[18].IMUX_IMUX[47] |
| DB[76] | in | CELL[19].IMUX_IMUX[44] |
| DB[77] | in | CELL[19].IMUX_IMUX[45] |
| DB[78] | in | CELL[19].IMUX_IMUX[46] |
| DB[79] | in | CELL[19].IMUX_IMUX[47] |
| DH[0] | in | CELL[19].IMUX_IMUX[42] |
| DH[1] | in | CELL[19].IMUX_IMUX[43] |
Bels BUFHCE
| Pin | Direction | BUFHCE_W[0] | BUFHCE_W[1] | BUFHCE_W[2] | BUFHCE_W[3] | BUFHCE_W[4] | BUFHCE_W[5] | BUFHCE_W[6] | BUFHCE_W[7] | BUFHCE_W[8] | BUFHCE_W[9] | BUFHCE_W[10] | BUFHCE_W[11] | BUFHCE_E[0] | BUFHCE_E[1] | BUFHCE_E[2] | BUFHCE_E[3] | BUFHCE_E[4] | BUFHCE_E[5] | BUFHCE_E[6] | BUFHCE_E[7] | BUFHCE_E[8] | BUFHCE_E[9] | BUFHCE_E[10] | BUFHCE_E[11] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| I | in | CELL[20].IMUX_BUFHCE_W[0] | CELL[20].IMUX_BUFHCE_W[1] | CELL[20].IMUX_BUFHCE_W[2] | CELL[20].IMUX_BUFHCE_W[3] | CELL[20].IMUX_BUFHCE_W[4] | CELL[20].IMUX_BUFHCE_W[5] | CELL[20].IMUX_BUFHCE_W[6] | CELL[20].IMUX_BUFHCE_W[7] | CELL[20].IMUX_BUFHCE_W[8] | CELL[20].IMUX_BUFHCE_W[9] | CELL[20].IMUX_BUFHCE_W[10] | CELL[20].IMUX_BUFHCE_W[11] | CELL[20].IMUX_BUFHCE_E[0] | CELL[20].IMUX_BUFHCE_E[1] | CELL[20].IMUX_BUFHCE_E[2] | CELL[20].IMUX_BUFHCE_E[3] | CELL[20].IMUX_BUFHCE_E[4] | CELL[20].IMUX_BUFHCE_E[5] | CELL[20].IMUX_BUFHCE_E[6] | CELL[20].IMUX_BUFHCE_E[7] | CELL[20].IMUX_BUFHCE_E[8] | CELL[20].IMUX_BUFHCE_E[9] | CELL[20].IMUX_BUFHCE_E[10] | CELL[20].IMUX_BUFHCE_E[11] |
| CE | in | CELL[19].IMUX_IMUX[0] invert by !MAIN[18][27][19] | CELL[19].IMUX_IMUX[1] invert by !MAIN[18][28][19] | CELL[19].IMUX_IMUX[2] invert by !MAIN[18][27][35] | CELL[19].IMUX_IMUX[3] invert by !MAIN[18][28][35] | CELL[19].IMUX_IMUX[4] invert by !MAIN[18][27][51] | CELL[19].IMUX_IMUX[5] invert by !MAIN[18][28][51] | CELL[20].IMUX_IMUX[0] invert by !MAIN[21][27][3] | CELL[20].IMUX_IMUX[1] invert by !MAIN[21][28][3] | CELL[20].IMUX_IMUX[2] invert by !MAIN[21][27][19] | CELL[20].IMUX_IMUX[3] invert by !MAIN[21][28][19] | CELL[20].IMUX_IMUX[4] invert by !MAIN[21][27][35] | CELL[20].IMUX_IMUX[5] invert by !MAIN[21][28][35] | CELL[19].IMUX_IMUX[6] invert by !MAIN[18][31][19] | CELL[19].IMUX_IMUX[7] invert by !MAIN[18][32][19] | CELL[19].IMUX_IMUX[8] invert by !MAIN[18][31][35] | CELL[19].IMUX_IMUX[9] invert by !MAIN[18][32][35] | CELL[19].IMUX_IMUX[10] invert by !MAIN[18][31][51] | CELL[19].IMUX_IMUX[11] invert by !MAIN[18][32][51] | CELL[20].IMUX_IMUX[6] invert by !MAIN[21][31][3] | CELL[20].IMUX_IMUX[7] invert by !MAIN[21][32][3] | CELL[20].IMUX_IMUX[8] invert by !MAIN[21][31][19] | CELL[20].IMUX_IMUX[9] invert by !MAIN[21][32][19] | CELL[20].IMUX_IMUX[10] invert by !MAIN[21][31][35] | CELL[20].IMUX_IMUX[11] invert by !MAIN[21][32][35] |
| O | out | CELL[20].HCLK_CMT_W[0] | CELL[20].HCLK_CMT_W[1] | CELL[20].HCLK_CMT_W[2] | CELL[20].HCLK_CMT_W[3] | CELL[20].HCLK_CMT_W[4] | CELL[20].HCLK_CMT_W[5] | CELL[20].HCLK_CMT_W[6] | CELL[20].HCLK_CMT_W[7] | CELL[20].HCLK_CMT_W[8] | CELL[20].HCLK_CMT_W[9] | CELL[20].HCLK_CMT_W[10] | CELL[20].HCLK_CMT_W[11] | CELL[20].HCLK_CMT_E[0] | CELL[20].HCLK_CMT_E[1] | CELL[20].HCLK_CMT_E[2] | CELL[20].HCLK_CMT_E[3] | CELL[20].HCLK_CMT_E[4] | CELL[20].HCLK_CMT_E[5] | CELL[20].HCLK_CMT_E[6] | CELL[20].HCLK_CMT_E[7] | CELL[20].HCLK_CMT_E[8] | CELL[20].HCLK_CMT_E[9] | CELL[20].HCLK_CMT_E[10] | CELL[20].HCLK_CMT_E[11] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[0].IMUX_IMUX[44] | PPR_FRAME.DB[0] |
| CELL[0].IMUX_IMUX[45] | PPR_FRAME.DB[1] |
| CELL[0].IMUX_IMUX[46] | PPR_FRAME.DB[2] |
| CELL[0].IMUX_IMUX[47] | PPR_FRAME.DB[3] |
| CELL[1].IMUX_IMUX[44] | PPR_FRAME.DB[4] |
| CELL[1].IMUX_IMUX[45] | PPR_FRAME.DB[5] |
| CELL[1].IMUX_IMUX[46] | PPR_FRAME.DB[6] |
| CELL[1].IMUX_IMUX[47] | PPR_FRAME.DB[7] |
| CELL[2].IMUX_CLK[0] | PLL[0].DCLK |
| CELL[2].IMUX_CLK[1] | PLL[0].PSCLK |
| CELL[2].IMUX_IMUX[44] | PPR_FRAME.DB[8] |
| CELL[2].IMUX_IMUX[45] | PPR_FRAME.DB[9] |
| CELL[2].IMUX_IMUX[46] | PPR_FRAME.DB[10] |
| CELL[2].IMUX_IMUX[47] | PPR_FRAME.DB[11] |
| CELL[2].OUT_BEL[0] | PLL[0].PSDONE |
| CELL[2].OUT_BEL[1] | PLL[0].DO[15] |
| CELL[2].OUT_BEL[2] | PLL[0].DO[11] |
| CELL[2].OUT_BEL[8] | PLL[0].LOCKED |
| CELL[2].OUT_BEL[9] | PLL[0].DO[14] |
| CELL[2].OUT_BEL[11] | PLL[0].DO[9] |
| CELL[2].OUT_BEL[15] | PLL[0].DO[10] |
| CELL[2].OUT_BEL[16] | PLL[0].DO[12] |
| CELL[2].OUT_BEL[17] | PLL[0].DO[8] |
| CELL[2].OUT_BEL[18] | PLL[0].DRDY |
| CELL[2].OUT_BEL[19] | PLL[0].DO[13] |
| CELL[3].IMUX_IMUX[7] | PLL[0].DI[9] |
| CELL[3].IMUX_IMUX[8] | PLL[0].RST |
| CELL[3].IMUX_IMUX[9] | PLL[0].DEN |
| CELL[3].IMUX_IMUX[10] | PLL[0].DWE |
| CELL[3].IMUX_IMUX[11] | PLL[0].CLKINSEL |
| CELL[3].IMUX_IMUX[12] | PLL[0].DI[14] |
| CELL[3].IMUX_IMUX[13] | PLL[0].DI[12] |
| CELL[3].IMUX_IMUX[22] | PLL[0].DI[10] |
| CELL[3].IMUX_IMUX[32] | PLL[0].PSINCDEC |
| CELL[3].IMUX_IMUX[33] | PLL[0].PSEN |
| CELL[3].IMUX_IMUX[34] | PLL[0].PWRDWN |
| CELL[3].IMUX_IMUX[35] | PLL[0].DI[15] |
| CELL[3].IMUX_IMUX[36] | PLL[0].DI[13] |
| CELL[3].IMUX_IMUX[37] | PLL[0].DI[11] |
| CELL[3].IMUX_IMUX[39] | PLL[0].DI[8] |
| CELL[3].IMUX_IMUX[44] | PPR_FRAME.DB[12] |
| CELL[3].IMUX_IMUX[45] | PPR_FRAME.DB[13] |
| CELL[3].IMUX_IMUX[46] | PPR_FRAME.DB[14] |
| CELL[3].IMUX_IMUX[47] | PPR_FRAME.DB[15] |
| CELL[3].OUT_BEL[0] | PLL[0].DO[6] |
| CELL[3].OUT_BEL[1] | PLL[0].DO[5] |
| CELL[3].OUT_BEL[2] | PLL[0].DO[2] |
| CELL[3].OUT_BEL[3] | PLL[0].DO[1] |
| CELL[3].OUT_BEL[4] | PLL[0].DO[7] |
| CELL[3].OUT_BEL[5] | PLL[0].DO[4] |
| CELL[3].OUT_BEL[6] | PLL[0].DO[3] |
| CELL[3].OUT_BEL[7] | PLL[0].DO[0] |
| CELL[4].IMUX_IMUX[10] | PLL[0].DI[5] |
| CELL[4].IMUX_IMUX[11] | PLL[0].DI[4] |
| CELL[4].IMUX_IMUX[12] | PLL[0].DI[3] |
| CELL[4].IMUX_IMUX[13] | PLL[0].DI[2] |
| CELL[4].IMUX_IMUX[14] | PLL[0].DI[1] |
| CELL[4].IMUX_IMUX[15] | PLL[0].DI[0] |
| CELL[4].IMUX_IMUX[16] | PLL[0].DI[7] |
| CELL[4].IMUX_IMUX[17] | PLL[0].DI[6] |
| CELL[4].IMUX_IMUX[44] | PPR_FRAME.DB[16] |
| CELL[4].IMUX_IMUX[45] | PPR_FRAME.DB[17] |
| CELL[4].IMUX_IMUX[46] | PPR_FRAME.DB[18] |
| CELL[4].IMUX_IMUX[47] | PPR_FRAME.DB[19] |
| CELL[4].OUT_BEL[0] | PLL[0].CLKFBSTOPPED |
| CELL[4].OUT_BEL[1] | PLL[0].TESTOUT[31] |
| CELL[4].OUT_BEL[2] | PLL[0].TESTOUT[28] |
| CELL[4].OUT_BEL[3] | PLL[0].TESTOUT[27] |
| CELL[4].OUT_BEL[4] | PLL[0].CLKINSTOPPED |
| CELL[4].OUT_BEL[5] | PLL[0].TESTOUT[30] |
| CELL[4].OUT_BEL[6] | PLL[0].TESTOUT[29] |
| CELL[4].OUT_BEL[7] | PLL[0].TESTOUT[26] |
| CELL[5].IMUX_IMUX[5] | PLL[0].DADDR[2] |
| CELL[5].IMUX_IMUX[6] | PLL[0].DADDR[1] |
| CELL[5].IMUX_IMUX[7] | PLL[0].DADDR[0] |
| CELL[5].IMUX_IMUX[40] | PLL[0].DADDR[6] |
| CELL[5].IMUX_IMUX[41] | PLL[0].DADDR[5] |
| CELL[5].IMUX_IMUX[42] | PLL[0].DADDR[4] |
| CELL[5].IMUX_IMUX[43] | PLL[0].DADDR[3] |
| CELL[5].IMUX_IMUX[44] | PPR_FRAME.DB[20] |
| CELL[5].IMUX_IMUX[45] | PPR_FRAME.DB[21] |
| CELL[5].IMUX_IMUX[46] | PPR_FRAME.DB[22] |
| CELL[5].IMUX_IMUX[47] | PPR_FRAME.DB[23] |
| CELL[5].OUT_BEL[0] | PLL[0].TESTOUT[24] |
| CELL[5].OUT_BEL[1] | PLL[0].TESTOUT[23] |
| CELL[5].OUT_BEL[2] | PLL[0].TESTOUT[20] |
| CELL[5].OUT_BEL[3] | PLL[0].TESTOUT[19] |
| CELL[5].OUT_BEL[4] | PLL[0].TESTOUT[25] |
| CELL[5].OUT_BEL[5] | PLL[0].TESTOUT[22] |
| CELL[5].OUT_BEL[6] | PLL[0].TESTOUT[21] |
| CELL[5].OUT_BEL[7] | PLL[0].TESTOUT[18] |
| CELL[6].IMUX_IMUX[44] | PPR_FRAME.DB[24] |
| CELL[6].IMUX_IMUX[45] | PPR_FRAME.DB[25] |
| CELL[6].IMUX_IMUX[46] | PPR_FRAME.DB[26] |
| CELL[6].IMUX_IMUX[47] | PPR_FRAME.DB[27] |
| CELL[6].OUT_BEL[0] | PLL[0].TESTOUT[16] |
| CELL[6].OUT_BEL[1] | PLL[0].TESTOUT[15] |
| CELL[6].OUT_BEL[2] | PLL[0].TESTOUT[12] |
| CELL[6].OUT_BEL[3] | PLL[0].TESTOUT[11] |
| CELL[6].OUT_BEL[4] | PLL[0].TESTOUT[17] |
| CELL[6].OUT_BEL[5] | PLL[0].TESTOUT[14] |
| CELL[6].OUT_BEL[6] | PLL[0].TESTOUT[13] |
| CELL[6].OUT_BEL[7] | PLL[0].TESTOUT[10] |
| CELL[7].IMUX_IMUX[5] | PLL[0].TESTIN[17] |
| CELL[7].IMUX_IMUX[6] | PLL[0].TESTIN[14] |
| CELL[7].IMUX_IMUX[7] | PLL[0].TESTIN[11] |
| CELL[7].IMUX_IMUX[8] | PLL[0].TESTIN[31] |
| CELL[7].IMUX_IMUX[9] | PLL[0].TESTIN[28] |
| CELL[7].IMUX_IMUX[10] | PLL[0].TESTIN[25] |
| CELL[7].IMUX_IMUX[11] | PLL[0].TESTIN[22] |
| CELL[7].IMUX_IMUX[12] | PLL[0].TESTIN[19] |
| CELL[7].IMUX_IMUX[21] | PLL[0].TESTIN[16] |
| CELL[7].IMUX_IMUX[22] | PLL[0].TESTIN[13] |
| CELL[7].IMUX_IMUX[23] | PLL[0].TESTIN[10] |
| CELL[7].IMUX_IMUX[24] | PLL[0].TESTIN[30] |
| CELL[7].IMUX_IMUX[25] | PLL[0].TESTIN[27] |
| CELL[7].IMUX_IMUX[26] | PLL[0].TESTIN[24] |
| CELL[7].IMUX_IMUX[27] | PLL[0].TESTIN[21] |
| CELL[7].IMUX_IMUX[28] | PLL[0].TESTIN[18] |
| CELL[7].IMUX_IMUX[37] | PLL[0].TESTIN[15] |
| CELL[7].IMUX_IMUX[38] | PLL[0].TESTIN[12] |
| CELL[7].IMUX_IMUX[39] | PLL[0].TESTIN[9] |
| CELL[7].IMUX_IMUX[40] | PLL[0].TESTIN[29] |
| CELL[7].IMUX_IMUX[41] | PLL[0].TESTIN[26] |
| CELL[7].IMUX_IMUX[42] | PLL[0].TESTIN[23] |
| CELL[7].IMUX_IMUX[43] | PLL[0].TESTIN[20] |
| CELL[7].IMUX_IMUX[44] | PPR_FRAME.DB[28] |
| CELL[7].IMUX_IMUX[45] | PPR_FRAME.DB[29] |
| CELL[7].IMUX_IMUX[46] | PPR_FRAME.DB[30] |
| CELL[7].IMUX_IMUX[47] | PPR_FRAME.DB[31] |
| CELL[7].OUT_BEL[0] | PLL[0].TESTOUT[8] |
| CELL[7].OUT_BEL[1] | PLL[0].TESTOUT[7] |
| CELL[7].OUT_BEL[2] | PLL[0].TESTOUT[4] |
| CELL[7].OUT_BEL[3] | PLL[0].TESTOUT[3] |
| CELL[7].OUT_BEL[4] | PLL[0].TESTOUT[9] |
| CELL[7].OUT_BEL[5] | PLL[0].TESTOUT[6] |
| CELL[7].OUT_BEL[6] | PLL[0].TESTOUT[5] |
| CELL[7].OUT_BEL[7] | PLL[0].TESTOUT[2] |
| CELL[8].IMUX_IMUX[8] | PLL[0].TESTIN[8] |
| CELL[8].IMUX_IMUX[9] | PLL[0].TESTIN[6] |
| CELL[8].IMUX_IMUX[10] | PLL[0].TESTIN[4] |
| CELL[8].IMUX_IMUX[11] | PLL[0].TESTIN[2] |
| CELL[8].IMUX_IMUX[24] | PLL[0].TESTIN[7] |
| CELL[8].IMUX_IMUX[25] | PLL[0].TESTIN[5] |
| CELL[8].IMUX_IMUX[26] | PLL[0].TESTIN[3] |
| CELL[8].IMUX_IMUX[27] | PLL[0].TESTIN[1] |
| CELL[8].IMUX_IMUX[44] | PPR_FRAME.DB[32] |
| CELL[8].IMUX_IMUX[45] | PPR_FRAME.DB[33] |
| CELL[8].IMUX_IMUX[46] | PPR_FRAME.DB[34] |
| CELL[8].IMUX_IMUX[47] | PPR_FRAME.DB[35] |
| CELL[8].OUT_BEL[0] | PLL[0].TESTOUT[0] |
| CELL[8].OUT_BEL[1] | PLL[0].TESTOUT[63] |
| CELL[8].OUT_BEL[2] | PLL[0].TESTOUT[60] |
| CELL[8].OUT_BEL[3] | PLL[0].TESTOUT[59] |
| CELL[8].OUT_BEL[4] | PLL[0].TESTOUT[1] |
| CELL[8].OUT_BEL[5] | PLL[0].TESTOUT[62] |
| CELL[8].OUT_BEL[6] | PLL[0].TESTOUT[61] |
| CELL[8].OUT_BEL[7] | PLL[0].TESTOUT[58] |
| CELL[9].IMUX_IMUX[44] | PPR_FRAME.DB[36] |
| CELL[9].IMUX_IMUX[45] | PPR_FRAME.DB[37] |
| CELL[9].IMUX_IMUX[46] | PPR_FRAME.DB[38] |
| CELL[9].IMUX_IMUX[47] | PPR_FRAME.DB[39] |
| CELL[9].OUT_BEL[0] | PLL[0].TESTOUT[56] |
| CELL[9].OUT_BEL[1] | PLL[0].TESTOUT[55] |
| CELL[9].OUT_BEL[2] | PLL[0].TESTOUT[52] |
| CELL[9].OUT_BEL[3] | PLL[0].TESTOUT[51] |
| CELL[9].OUT_BEL[4] | PLL[0].TESTOUT[57] |
| CELL[9].OUT_BEL[5] | PLL[0].TESTOUT[54] |
| CELL[9].OUT_BEL[6] | PLL[0].TESTOUT[53] |
| CELL[9].OUT_BEL[7] | PLL[0].TESTOUT[50] |
| CELL[10].IMUX_IMUX[44] | PPR_FRAME.DB[40] |
| CELL[10].IMUX_IMUX[45] | PPR_FRAME.DB[41] |
| CELL[10].IMUX_IMUX[46] | PPR_FRAME.DB[42] |
| CELL[10].IMUX_IMUX[47] | PPR_FRAME.DB[43] |
| CELL[10].OUT_BEL[0] | PLL[0].TESTOUT[48] |
| CELL[10].OUT_BEL[1] | PLL[0].TESTOUT[47] |
| CELL[10].OUT_BEL[2] | PLL[0].TESTOUT[44] |
| CELL[10].OUT_BEL[3] | PLL[0].TESTOUT[43] |
| CELL[10].OUT_BEL[4] | PLL[0].TESTOUT[49] |
| CELL[10].OUT_BEL[5] | PLL[0].TESTOUT[46] |
| CELL[10].OUT_BEL[6] | PLL[0].TESTOUT[45] |
| CELL[10].OUT_BEL[7] | PLL[0].TESTOUT[42] |
| CELL[11].IMUX_IMUX[44] | PPR_FRAME.DB[44] |
| CELL[11].IMUX_IMUX[45] | PPR_FRAME.DB[45] |
| CELL[11].IMUX_IMUX[46] | PPR_FRAME.DB[46] |
| CELL[11].IMUX_IMUX[47] | PPR_FRAME.DB[47] |
| CELL[12].IMUX_IMUX[44] | PPR_FRAME.DB[48] |
| CELL[12].IMUX_IMUX[45] | PPR_FRAME.DB[49] |
| CELL[12].IMUX_IMUX[46] | PPR_FRAME.DB[50] |
| CELL[12].IMUX_IMUX[47] | PPR_FRAME.DB[51] |
| CELL[13].IMUX_IMUX[44] | PPR_FRAME.DB[52] |
| CELL[13].IMUX_IMUX[45] | PPR_FRAME.DB[53] |
| CELL[13].IMUX_IMUX[46] | PPR_FRAME.DB[54] |
| CELL[13].IMUX_IMUX[47] | PPR_FRAME.DB[55] |
| CELL[14].IMUX_IMUX[44] | PPR_FRAME.DB[56] |
| CELL[14].IMUX_IMUX[45] | PPR_FRAME.DB[57] |
| CELL[14].IMUX_IMUX[46] | PPR_FRAME.DB[58] |
| CELL[14].IMUX_IMUX[47] | PPR_FRAME.DB[59] |
| CELL[15].IMUX_IMUX[44] | PPR_FRAME.DB[60] |
| CELL[15].IMUX_IMUX[45] | PPR_FRAME.DB[61] |
| CELL[15].IMUX_IMUX[46] | PPR_FRAME.DB[62] |
| CELL[15].IMUX_IMUX[47] | PPR_FRAME.DB[63] |
| CELL[16].IMUX_IMUX[44] | PPR_FRAME.DB[64] |
| CELL[16].IMUX_IMUX[45] | PPR_FRAME.DB[65] |
| CELL[16].IMUX_IMUX[46] | PPR_FRAME.DB[66] |
| CELL[16].IMUX_IMUX[47] | PPR_FRAME.DB[67] |
| CELL[17].IMUX_IMUX[14] | PLL[0].TESTIN[0] |
| CELL[17].IMUX_IMUX[44] | PPR_FRAME.DB[68] |
| CELL[17].IMUX_IMUX[45] | PPR_FRAME.DB[69] |
| CELL[17].IMUX_IMUX[46] | PPR_FRAME.DB[70] |
| CELL[17].IMUX_IMUX[47] | PPR_FRAME.DB[71] |
| CELL[17].IMUX_SPEC[3] | PLL[0].TESTOUT[32], PLL[0].TESTOUT[33], PLL[0].TESTOUT[34], PLL[0].TESTOUT[35], PLL[0].TESTOUT[36], PLL[0].TESTOUT[37], PLL[0].TESTOUT[38], PLL[0].TESTOUT[39], PLL[0].TESTOUT[40], PLL[0].TESTOUT[41] |
| CELL[18].IMUX_IMUX[44] | PPR_FRAME.DB[72] |
| CELL[18].IMUX_IMUX[45] | PPR_FRAME.DB[73] |
| CELL[18].IMUX_IMUX[46] | PPR_FRAME.DB[74] |
| CELL[18].IMUX_IMUX[47] | PPR_FRAME.DB[75] |
| CELL[19].IMUX_IMUX[0] | BUFHCE_W[0].CE |
| CELL[19].IMUX_IMUX[1] | BUFHCE_W[1].CE |
| CELL[19].IMUX_IMUX[2] | BUFHCE_W[2].CE |
| CELL[19].IMUX_IMUX[3] | BUFHCE_W[3].CE |
| CELL[19].IMUX_IMUX[4] | BUFHCE_W[4].CE |
| CELL[19].IMUX_IMUX[5] | BUFHCE_W[5].CE |
| CELL[19].IMUX_IMUX[6] | BUFHCE_E[0].CE |
| CELL[19].IMUX_IMUX[7] | BUFHCE_E[1].CE |
| CELL[19].IMUX_IMUX[8] | BUFHCE_E[2].CE |
| CELL[19].IMUX_IMUX[9] | BUFHCE_E[3].CE |
| CELL[19].IMUX_IMUX[10] | BUFHCE_E[4].CE |
| CELL[19].IMUX_IMUX[11] | BUFHCE_E[5].CE |
| CELL[19].IMUX_IMUX[42] | PPR_FRAME.DH[0] |
| CELL[19].IMUX_IMUX[43] | PPR_FRAME.DH[1] |
| CELL[19].IMUX_IMUX[44] | PPR_FRAME.DB[76] |
| CELL[19].IMUX_IMUX[45] | PPR_FRAME.DB[77] |
| CELL[19].IMUX_IMUX[46] | PPR_FRAME.DB[78] |
| CELL[19].IMUX_IMUX[47] | PPR_FRAME.DB[79] |
| CELL[20].IMUX_IMUX[0] | BUFHCE_W[6].CE |
| CELL[20].IMUX_IMUX[1] | BUFHCE_W[7].CE |
| CELL[20].IMUX_IMUX[2] | BUFHCE_W[8].CE |
| CELL[20].IMUX_IMUX[3] | BUFHCE_W[9].CE |
| CELL[20].IMUX_IMUX[4] | BUFHCE_W[10].CE |
| CELL[20].IMUX_IMUX[5] | BUFHCE_W[11].CE |
| CELL[20].IMUX_IMUX[6] | BUFHCE_E[6].CE |
| CELL[20].IMUX_IMUX[7] | BUFHCE_E[7].CE |
| CELL[20].IMUX_IMUX[8] | BUFHCE_E[8].CE |
| CELL[20].IMUX_IMUX[9] | BUFHCE_E[9].CE |
| CELL[20].IMUX_IMUX[10] | BUFHCE_E[10].CE |
| CELL[20].IMUX_IMUX[11] | BUFHCE_E[11].CE |
| CELL[20].IMUX_IMUX[44] | PPR_FRAME.DA[0] |
| CELL[20].IMUX_IMUX[45] | PPR_FRAME.DA[1] |
| CELL[20].IMUX_IMUX[46] | PPR_FRAME.DA[2] |
| CELL[20].IMUX_IMUX[47] | PPR_FRAME.DA[3] |
| CELL[20].IMUX_BUFHCE_W[0] | BUFHCE_W[0].I |
| CELL[20].IMUX_BUFHCE_W[1] | BUFHCE_W[1].I |
| CELL[20].IMUX_BUFHCE_W[2] | BUFHCE_W[2].I |
| CELL[20].IMUX_BUFHCE_W[3] | BUFHCE_W[3].I |
| CELL[20].IMUX_BUFHCE_W[4] | BUFHCE_W[4].I |
| CELL[20].IMUX_BUFHCE_W[5] | BUFHCE_W[5].I |
| CELL[20].IMUX_BUFHCE_W[6] | BUFHCE_W[6].I |
| CELL[20].IMUX_BUFHCE_W[7] | BUFHCE_W[7].I |
| CELL[20].IMUX_BUFHCE_W[8] | BUFHCE_W[8].I |
| CELL[20].IMUX_BUFHCE_W[9] | BUFHCE_W[9].I |
| CELL[20].IMUX_BUFHCE_W[10] | BUFHCE_W[10].I |
| CELL[20].IMUX_BUFHCE_W[11] | BUFHCE_W[11].I |
| CELL[20].IMUX_BUFHCE_E[0] | BUFHCE_E[0].I |
| CELL[20].IMUX_BUFHCE_E[1] | BUFHCE_E[1].I |
| CELL[20].IMUX_BUFHCE_E[2] | BUFHCE_E[2].I |
| CELL[20].IMUX_BUFHCE_E[3] | BUFHCE_E[3].I |
| CELL[20].IMUX_BUFHCE_E[4] | BUFHCE_E[4].I |
| CELL[20].IMUX_BUFHCE_E[5] | BUFHCE_E[5].I |
| CELL[20].IMUX_BUFHCE_E[6] | BUFHCE_E[6].I |
| CELL[20].IMUX_BUFHCE_E[7] | BUFHCE_E[7].I |
| CELL[20].IMUX_BUFHCE_E[8] | BUFHCE_E[8].I |
| CELL[20].IMUX_BUFHCE_E[9] | BUFHCE_E[9].I |
| CELL[20].IMUX_BUFHCE_E[10] | BUFHCE_E[10].I |
| CELL[20].IMUX_BUFHCE_E[11] | BUFHCE_E[11].I |
| CELL[20].HCLK_CMT_W[0] | BUFHCE_W[0].O |
| CELL[20].HCLK_CMT_W[1] | BUFHCE_W[1].O |
| CELL[20].HCLK_CMT_W[2] | BUFHCE_W[2].O |
| CELL[20].HCLK_CMT_W[3] | BUFHCE_W[3].O |
| CELL[20].HCLK_CMT_W[4] | BUFHCE_W[4].O |
| CELL[20].HCLK_CMT_W[5] | BUFHCE_W[5].O |
| CELL[20].HCLK_CMT_W[6] | BUFHCE_W[6].O |
| CELL[20].HCLK_CMT_W[7] | BUFHCE_W[7].O |
| CELL[20].HCLK_CMT_W[8] | BUFHCE_W[8].O |
| CELL[20].HCLK_CMT_W[9] | BUFHCE_W[9].O |
| CELL[20].HCLK_CMT_W[10] | BUFHCE_W[10].O |
| CELL[20].HCLK_CMT_W[11] | BUFHCE_W[11].O |
| CELL[20].HCLK_CMT_E[0] | BUFHCE_E[0].O |
| CELL[20].HCLK_CMT_E[1] | BUFHCE_E[1].O |
| CELL[20].HCLK_CMT_E[2] | BUFHCE_E[2].O |
| CELL[20].HCLK_CMT_E[3] | BUFHCE_E[3].O |
| CELL[20].HCLK_CMT_E[4] | BUFHCE_E[4].O |
| CELL[20].HCLK_CMT_E[5] | BUFHCE_E[5].O |
| CELL[20].HCLK_CMT_E[6] | BUFHCE_E[6].O |
| CELL[20].HCLK_CMT_E[7] | BUFHCE_E[7].O |
| CELL[20].HCLK_CMT_E[8] | BUFHCE_E[8].O |
| CELL[20].HCLK_CMT_E[9] | BUFHCE_E[9].O |
| CELL[20].HCLK_CMT_E[10] | BUFHCE_E[10].O |
| CELL[20].HCLK_CMT_E[11] | BUFHCE_E[11].O |
| CELL[20].IMUX_PLL_CLKIN1[0] | PLL[0].CLKIN1 |
| CELL[20].IMUX_PLL_CLKIN1[1] | PLL[1].CLKIN1 |
| CELL[20].IMUX_PLL_CLKIN2[0] | PLL[0].CLKIN2 |
| CELL[20].IMUX_PLL_CLKIN2[1] | PLL[1].CLKIN2 |
| CELL[20].IMUX_PLL_CLKFB[0] | PLL[0].CLKFBIN |
| CELL[20].IMUX_PLL_CLKFB[1] | PLL[1].CLKFBIN |
| CELL[20].OUT_PLL_S[0] | PLL[0].CLKOUT0 |
| CELL[20].OUT_PLL_S[1] | PLL[0].CLKOUT0B |
| CELL[20].OUT_PLL_S[2] | PLL[0].CLKOUT1 |
| CELL[20].OUT_PLL_S[3] | PLL[0].CLKOUT1B |
| CELL[20].OUT_PLL_S[4] | PLL[0].CLKOUT2 |
| CELL[20].OUT_PLL_S[5] | PLL[0].CLKOUT2B |
| CELL[20].OUT_PLL_S[6] | PLL[0].CLKOUT3 |
| CELL[20].OUT_PLL_S[7] | PLL[0].CLKOUT3B |
| CELL[20].OUT_PLL_S[8] | PLL[0].CLKOUT4 |
| CELL[20].OUT_PLL_S[9] | PLL[0].CLKOUT5 |
| CELL[20].OUT_PLL_S[10] | PLL[0].CLKOUT6 |
| CELL[20].OUT_PLL_S[11] | PLL[0].CLKFBOUT |
| CELL[20].OUT_PLL_S[12] | PLL[0].CLKFBOUTB |
| CELL[20].OUT_PLL_S[13] | PLL[0].TMUXOUT |
| CELL[20].OUT_PLL_N[0] | PLL[1].CLKOUT0 |
| CELL[20].OUT_PLL_N[1] | PLL[1].CLKOUT0B |
| CELL[20].OUT_PLL_N[2] | PLL[1].CLKOUT1 |
| CELL[20].OUT_PLL_N[3] | PLL[1].CLKOUT1B |
| CELL[20].OUT_PLL_N[4] | PLL[1].CLKOUT2 |
| CELL[20].OUT_PLL_N[5] | PLL[1].CLKOUT2B |
| CELL[20].OUT_PLL_N[6] | PLL[1].CLKOUT3 |
| CELL[20].OUT_PLL_N[7] | PLL[1].CLKOUT3B |
| CELL[20].OUT_PLL_N[8] | PLL[1].CLKOUT4 |
| CELL[20].OUT_PLL_N[9] | PLL[1].CLKOUT5 |
| CELL[20].OUT_PLL_N[10] | PLL[1].CLKOUT6 |
| CELL[20].OUT_PLL_N[11] | PLL[1].CLKFBOUT |
| CELL[20].OUT_PLL_N[12] | PLL[1].CLKFBOUTB |
| CELL[20].OUT_PLL_N[13] | PLL[1].TMUXOUT |
| CELL[20].OMUX_PLL_CASC[0] | PLL[1].CLKIN_CASC, PLL[0].CLKFB_CASC |
| CELL[20].OMUX_PLL_CASC[1] | PLL[0].CLKIN_CASC, PLL[1].CLKFB_CASC |
| CELL[21].IMUX_IMUX[44] | PPR_FRAME.DA[4] |
| CELL[21].IMUX_IMUX[45] | PPR_FRAME.DA[5] |
| CELL[21].IMUX_IMUX[46] | PPR_FRAME.DA[6] |
| CELL[21].IMUX_IMUX[47] | PPR_FRAME.DA[7] |
| CELL[22].IMUX_IMUX[33] | PLL[1].TESTIN[0] |
| CELL[22].IMUX_IMUX[44] | PPR_FRAME.DA[8] |
| CELL[22].IMUX_IMUX[45] | PPR_FRAME.DA[9] |
| CELL[22].IMUX_IMUX[46] | PPR_FRAME.DA[10] |
| CELL[22].IMUX_IMUX[47] | PPR_FRAME.DA[11] |
| CELL[23].IMUX_IMUX[44] | PPR_FRAME.DA[12] |
| CELL[23].IMUX_IMUX[45] | PPR_FRAME.DA[13] |
| CELL[23].IMUX_IMUX[46] | PPR_FRAME.DA[14] |
| CELL[23].IMUX_IMUX[47] | PPR_FRAME.DA[15] |
| CELL[24].IMUX_IMUX[44] | PPR_FRAME.DA[16] |
| CELL[24].IMUX_IMUX[45] | PPR_FRAME.DA[17] |
| CELL[24].IMUX_IMUX[46] | PPR_FRAME.DA[18] |
| CELL[24].IMUX_IMUX[47] | PPR_FRAME.DA[19] |
| CELL[25].IMUX_IMUX[44] | PPR_FRAME.DA[20] |
| CELL[25].IMUX_IMUX[45] | PPR_FRAME.DA[21] |
| CELL[25].IMUX_IMUX[46] | PPR_FRAME.DA[22] |
| CELL[25].IMUX_IMUX[47] | PPR_FRAME.DA[23] |
| CELL[26].IMUX_IMUX[44] | PPR_FRAME.DA[24] |
| CELL[26].IMUX_IMUX[45] | PPR_FRAME.DA[25] |
| CELL[26].IMUX_IMUX[46] | PPR_FRAME.DA[26] |
| CELL[26].IMUX_IMUX[47] | PPR_FRAME.DA[27] |
| CELL[27].IMUX_IMUX[44] | PPR_FRAME.DA[28] |
| CELL[27].IMUX_IMUX[45] | PPR_FRAME.DA[29] |
| CELL[27].IMUX_IMUX[46] | PPR_FRAME.DA[30] |
| CELL[27].IMUX_IMUX[47] | PPR_FRAME.DA[31] |
| CELL[27].OUT_BEL[3] | PLL[1].TESTOUT[32] |
| CELL[27].OUT_BEL[7] | PLL[1].TESTOUT[33] |
| CELL[28].IMUX_IMUX[44] | PPR_FRAME.DA[32] |
| CELL[28].IMUX_IMUX[45] | PPR_FRAME.DA[33] |
| CELL[28].IMUX_IMUX[46] | PPR_FRAME.DA[34] |
| CELL[28].IMUX_IMUX[47] | PPR_FRAME.DA[35] |
| CELL[29].IMUX_IMUX[44] | PPR_FRAME.DA[36] |
| CELL[29].IMUX_IMUX[45] | PPR_FRAME.DA[37] |
| CELL[29].IMUX_IMUX[46] | PPR_FRAME.DA[38] |
| CELL[29].IMUX_IMUX[47] | PPR_FRAME.DA[39] |
| CELL[29].OUT_BEL[0] | PLL[1].TESTOUT[43] |
| CELL[29].OUT_BEL[1] | PLL[1].TESTOUT[44] |
| CELL[29].OUT_BEL[2] | PLL[1].TESTOUT[47] |
| CELL[29].OUT_BEL[3] | PLL[1].TESTOUT[48] |
| CELL[29].OUT_BEL[4] | PLL[1].TESTOUT[42] |
| CELL[29].OUT_BEL[5] | PLL[1].TESTOUT[45] |
| CELL[29].OUT_BEL[6] | PLL[1].TESTOUT[46] |
| CELL[29].OUT_BEL[7] | PLL[1].TESTOUT[49] |
| CELL[30].IMUX_IMUX[44] | PPR_FRAME.DA[40] |
| CELL[30].IMUX_IMUX[45] | PPR_FRAME.DA[41] |
| CELL[30].IMUX_IMUX[46] | PPR_FRAME.DA[42] |
| CELL[30].IMUX_IMUX[47] | PPR_FRAME.DA[43] |
| CELL[30].OUT_BEL[0] | PLL[1].TESTOUT[51] |
| CELL[30].OUT_BEL[1] | PLL[1].TESTOUT[52] |
| CELL[30].OUT_BEL[2] | PLL[1].TESTOUT[55] |
| CELL[30].OUT_BEL[3] | PLL[1].TESTOUT[56] |
| CELL[30].OUT_BEL[4] | PLL[1].TESTOUT[50] |
| CELL[30].OUT_BEL[5] | PLL[1].TESTOUT[53] |
| CELL[30].OUT_BEL[6] | PLL[1].TESTOUT[54] |
| CELL[30].OUT_BEL[7] | PLL[1].TESTOUT[57] |
| CELL[31].IMUX_IMUX[20] | PLL[1].TESTIN[1] |
| CELL[31].IMUX_IMUX[21] | PLL[1].TESTIN[3] |
| CELL[31].IMUX_IMUX[22] | PLL[1].TESTIN[5] |
| CELL[31].IMUX_IMUX[23] | PLL[1].TESTIN[7] |
| CELL[31].IMUX_IMUX[36] | PLL[1].TESTIN[2] |
| CELL[31].IMUX_IMUX[37] | PLL[1].TESTIN[4] |
| CELL[31].IMUX_IMUX[38] | PLL[1].TESTIN[6] |
| CELL[31].IMUX_IMUX[39] | PLL[1].TESTIN[8] |
| CELL[31].IMUX_IMUX[44] | PPR_FRAME.DA[44] |
| CELL[31].IMUX_IMUX[45] | PPR_FRAME.DA[45] |
| CELL[31].IMUX_IMUX[46] | PPR_FRAME.DA[46] |
| CELL[31].IMUX_IMUX[47] | PPR_FRAME.DA[47] |
| CELL[31].OUT_BEL[0] | PLL[1].TESTOUT[59] |
| CELL[31].OUT_BEL[1] | PLL[1].TESTOUT[60] |
| CELL[31].OUT_BEL[2] | PLL[1].TESTOUT[63] |
| CELL[31].OUT_BEL[3] | PLL[1].TESTOUT[0] |
| CELL[31].OUT_BEL[4] | PLL[1].TESTOUT[58] |
| CELL[31].OUT_BEL[5] | PLL[1].TESTOUT[61] |
| CELL[31].OUT_BEL[6] | PLL[1].TESTOUT[62] |
| CELL[31].OUT_BEL[7] | PLL[1].TESTOUT[1] |
| CELL[32].IMUX_IMUX[4] | PLL[1].TESTIN[20] |
| CELL[32].IMUX_IMUX[5] | PLL[1].TESTIN[23] |
| CELL[32].IMUX_IMUX[6] | PLL[1].TESTIN[26] |
| CELL[32].IMUX_IMUX[7] | PLL[1].TESTIN[29] |
| CELL[32].IMUX_IMUX[8] | PLL[1].TESTIN[9] |
| CELL[32].IMUX_IMUX[9] | PLL[1].TESTIN[12] |
| CELL[32].IMUX_IMUX[10] | PLL[1].TESTIN[15] |
| CELL[32].IMUX_IMUX[19] | PLL[1].TESTIN[18] |
| CELL[32].IMUX_IMUX[20] | PLL[1].TESTIN[21] |
| CELL[32].IMUX_IMUX[21] | PLL[1].TESTIN[24] |
| CELL[32].IMUX_IMUX[22] | PLL[1].TESTIN[27] |
| CELL[32].IMUX_IMUX[23] | PLL[1].TESTIN[30] |
| CELL[32].IMUX_IMUX[24] | PLL[1].TESTIN[10] |
| CELL[32].IMUX_IMUX[25] | PLL[1].TESTIN[13] |
| CELL[32].IMUX_IMUX[26] | PLL[1].TESTIN[16] |
| CELL[32].IMUX_IMUX[35] | PLL[1].TESTIN[19] |
| CELL[32].IMUX_IMUX[36] | PLL[1].TESTIN[22] |
| CELL[32].IMUX_IMUX[37] | PLL[1].TESTIN[25] |
| CELL[32].IMUX_IMUX[38] | PLL[1].TESTIN[28] |
| CELL[32].IMUX_IMUX[39] | PLL[1].TESTIN[31] |
| CELL[32].IMUX_IMUX[40] | PLL[1].TESTIN[11] |
| CELL[32].IMUX_IMUX[41] | PLL[1].TESTIN[14] |
| CELL[32].IMUX_IMUX[42] | PLL[1].TESTIN[17] |
| CELL[32].IMUX_IMUX[44] | PPR_FRAME.DA[48] |
| CELL[32].IMUX_IMUX[45] | PPR_FRAME.DA[49] |
| CELL[32].IMUX_IMUX[46] | PPR_FRAME.DA[50] |
| CELL[32].IMUX_IMUX[47] | PPR_FRAME.DA[51] |
| CELL[32].OUT_BEL[0] | PLL[1].TESTOUT[3] |
| CELL[32].OUT_BEL[1] | PLL[1].TESTOUT[4] |
| CELL[32].OUT_BEL[2] | PLL[1].TESTOUT[7] |
| CELL[32].OUT_BEL[3] | PLL[1].TESTOUT[8] |
| CELL[32].OUT_BEL[4] | PLL[1].TESTOUT[2] |
| CELL[32].OUT_BEL[5] | PLL[1].TESTOUT[5] |
| CELL[32].OUT_BEL[6] | PLL[1].TESTOUT[6] |
| CELL[32].OUT_BEL[7] | PLL[1].TESTOUT[9] |
| CELL[33].IMUX_IMUX[44] | PPR_FRAME.DA[52] |
| CELL[33].IMUX_IMUX[45] | PPR_FRAME.DA[53] |
| CELL[33].IMUX_IMUX[46] | PPR_FRAME.DA[54] |
| CELL[33].IMUX_IMUX[47] | PPR_FRAME.DA[55] |
| CELL[33].OUT_BEL[0] | PLL[1].TESTOUT[11] |
| CELL[33].OUT_BEL[1] | PLL[1].TESTOUT[12] |
| CELL[33].OUT_BEL[2] | PLL[1].TESTOUT[15] |
| CELL[33].OUT_BEL[3] | PLL[1].TESTOUT[16] |
| CELL[33].OUT_BEL[4] | PLL[1].TESTOUT[10] |
| CELL[33].OUT_BEL[5] | PLL[1].TESTOUT[13] |
| CELL[33].OUT_BEL[6] | PLL[1].TESTOUT[14] |
| CELL[33].OUT_BEL[7] | PLL[1].TESTOUT[17] |
| CELL[34].IMUX_IMUX[4] | PLL[1].DADDR[3] |
| CELL[34].IMUX_IMUX[5] | PLL[1].DADDR[4] |
| CELL[34].IMUX_IMUX[6] | PLL[1].DADDR[5] |
| CELL[34].IMUX_IMUX[7] | PLL[1].DADDR[6] |
| CELL[34].IMUX_IMUX[40] | PLL[1].DADDR[0] |
| CELL[34].IMUX_IMUX[41] | PLL[1].DADDR[1] |
| CELL[34].IMUX_IMUX[42] | PLL[1].DADDR[2] |
| CELL[34].IMUX_IMUX[44] | PPR_FRAME.DA[56] |
| CELL[34].IMUX_IMUX[45] | PPR_FRAME.DA[57] |
| CELL[34].IMUX_IMUX[46] | PPR_FRAME.DA[58] |
| CELL[34].IMUX_IMUX[47] | PPR_FRAME.DA[59] |
| CELL[34].OUT_BEL[0] | PLL[1].TESTOUT[19] |
| CELL[34].OUT_BEL[1] | PLL[1].TESTOUT[20] |
| CELL[34].OUT_BEL[2] | PLL[1].TESTOUT[23] |
| CELL[34].OUT_BEL[3] | PLL[1].TESTOUT[24] |
| CELL[34].OUT_BEL[4] | PLL[1].TESTOUT[18] |
| CELL[34].OUT_BEL[5] | PLL[1].TESTOUT[21] |
| CELL[34].OUT_BEL[6] | PLL[1].TESTOUT[22] |
| CELL[34].OUT_BEL[7] | PLL[1].TESTOUT[25] |
| CELL[35].IMUX_IMUX[30] | PLL[1].DI[6] |
| CELL[35].IMUX_IMUX[31] | PLL[1].DI[7] |
| CELL[35].IMUX_IMUX[32] | PLL[1].DI[0] |
| CELL[35].IMUX_IMUX[33] | PLL[1].DI[1] |
| CELL[35].IMUX_IMUX[34] | PLL[1].DI[2] |
| CELL[35].IMUX_IMUX[35] | PLL[1].DI[3] |
| CELL[35].IMUX_IMUX[36] | PLL[1].DI[4] |
| CELL[35].IMUX_IMUX[37] | PLL[1].DI[5] |
| CELL[35].IMUX_IMUX[40] | PPR_FRAME.SHIFTB |
| CELL[35].IMUX_IMUX[41] | PPR_FRAME.UPDATEB |
| CELL[35].IMUX_IMUX[42] | PPR_FRAME.ENB |
| CELL[35].IMUX_IMUX[43] | PPR_FRAME.CTLB |
| CELL[35].IMUX_IMUX[44] | PPR_FRAME.DA[60] |
| CELL[35].IMUX_IMUX[45] | PPR_FRAME.DA[61] |
| CELL[35].IMUX_IMUX[46] | PPR_FRAME.DA[62] |
| CELL[35].IMUX_IMUX[47] | PPR_FRAME.DA[63] |
| CELL[35].OUT_BEL[0] | PLL[1].TESTOUT[27] |
| CELL[35].OUT_BEL[1] | PLL[1].TESTOUT[28] |
| CELL[35].OUT_BEL[2] | PLL[1].TESTOUT[31] |
| CELL[35].OUT_BEL[3] | PLL[1].CLKFBSTOPPED |
| CELL[35].OUT_BEL[4] | PLL[1].TESTOUT[26] |
| CELL[35].OUT_BEL[5] | PLL[1].TESTOUT[29] |
| CELL[35].OUT_BEL[6] | PLL[1].TESTOUT[30] |
| CELL[35].OUT_BEL[7] | PLL[1].CLKINSTOPPED |
| CELL[36].IMUX_IMUX[8] | PLL[1].DI[8] |
| CELL[36].IMUX_IMUX[10] | PLL[1].DI[11] |
| CELL[36].IMUX_IMUX[11] | PLL[1].DI[13] |
| CELL[36].IMUX_IMUX[12] | PLL[1].DI[15] |
| CELL[36].IMUX_IMUX[13] | PLL[1].PWRDWN |
| CELL[36].IMUX_IMUX[14] | PLL[1].PSEN |
| CELL[36].IMUX_IMUX[15] | PLL[1].PSINCDEC |
| CELL[36].IMUX_IMUX[25] | PLL[1].DI[10] |
| CELL[36].IMUX_IMUX[34] | PLL[1].DI[12] |
| CELL[36].IMUX_IMUX[35] | PLL[1].DI[14] |
| CELL[36].IMUX_IMUX[36] | PLL[1].CLKINSEL |
| CELL[36].IMUX_IMUX[37] | PLL[1].DWE |
| CELL[36].IMUX_IMUX[38] | PLL[1].DEN |
| CELL[36].IMUX_IMUX[39] | PLL[1].RST |
| CELL[36].IMUX_IMUX[40] | PLL[1].DI[9] |
| CELL[36].IMUX_IMUX[44] | PPR_FRAME.DA[64] |
| CELL[36].IMUX_IMUX[45] | PPR_FRAME.DA[65] |
| CELL[36].IMUX_IMUX[46] | PPR_FRAME.DA[66] |
| CELL[36].IMUX_IMUX[47] | PPR_FRAME.DA[67] |
| CELL[36].OUT_BEL[0] | PLL[1].DO[1] |
| CELL[36].OUT_BEL[1] | PLL[1].DO[2] |
| CELL[36].OUT_BEL[2] | PLL[1].DO[5] |
| CELL[36].OUT_BEL[3] | PLL[1].DO[6] |
| CELL[36].OUT_BEL[4] | PLL[1].DO[0] |
| CELL[36].OUT_BEL[5] | PLL[1].DO[3] |
| CELL[36].OUT_BEL[6] | PLL[1].DO[4] |
| CELL[36].OUT_BEL[7] | PLL[1].DO[7] |
| CELL[37].IMUX_CLK[0] | PLL[1].PSCLK |
| CELL[37].IMUX_CLK[1] | PLL[1].DCLK |
| CELL[37].IMUX_IMUX[44] | PPR_FRAME.DA[68] |
| CELL[37].IMUX_IMUX[45] | PPR_FRAME.DA[69] |
| CELL[37].IMUX_IMUX[46] | PPR_FRAME.DA[70] |
| CELL[37].IMUX_IMUX[47] | PPR_FRAME.DA[71] |
| CELL[37].OUT_BEL[1] | PLL[1].DO[11] |
| CELL[37].OUT_BEL[2] | PLL[1].DO[15] |
| CELL[37].OUT_BEL[3] | PLL[1].PSDONE |
| CELL[37].OUT_BEL[8] | PLL[1].DO[8] |
| CELL[37].OUT_BEL[9] | PLL[1].DO[12] |
| CELL[37].OUT_BEL[10] | PLL[1].DO[13] |
| CELL[37].OUT_BEL[11] | PLL[1].DRDY |
| CELL[37].OUT_BEL[16] | PLL[1].DO[14] |
| CELL[37].OUT_BEL[17] | PLL[1].LOCKED |
| CELL[37].OUT_BEL[18] | PLL[1].DO[9] |
| CELL[37].OUT_BEL[22] | PLL[1].DO[10] |
| CELL[37].IMUX_SPEC[3] | PLL[1].TESTOUT[34], PLL[1].TESTOUT[35], PLL[1].TESTOUT[36], PLL[1].TESTOUT[37], PLL[1].TESTOUT[38], PLL[1].TESTOUT[39], PLL[1].TESTOUT[40], PLL[1].TESTOUT[41] |
| CELL[38].IMUX_IMUX[44] | PPR_FRAME.DA[72] |
| CELL[38].IMUX_IMUX[45] | PPR_FRAME.DA[73] |
| CELL[38].IMUX_IMUX[46] | PPR_FRAME.DA[74] |
| CELL[38].IMUX_IMUX[47] | PPR_FRAME.DA[75] |
| CELL[39].IMUX_CLK[1] | PPR_FRAME.CLK |
| CELL[39].IMUX_IMUX[44] | PPR_FRAME.DA[76] |
| CELL[39].IMUX_IMUX[45] | PPR_FRAME.DA[77] |
| CELL[39].IMUX_IMUX[46] | PPR_FRAME.DA[78] |
| CELL[39].IMUX_IMUX[47] | PPR_FRAME.DA[79] |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 0 | PLL[0]: DRP[120] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 2 | PLL[0]: DRP[120] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 4 | PLL[0]: DRP[120] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 6 | PLL[0]: DRP[120] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 8 | PLL[0]: DRP[120] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 10 | PLL[0]: DRP[120] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 12 | PLL[0]: DRP[120] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[120] bit 14 | PLL[0]: DRP[120] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 0 | PLL[0]: DRP[121] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 2 | PLL[0]: DRP[121] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 4 | PLL[0]: DRP[121] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 6 | PLL[0]: DRP[121] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 8 | PLL[0]: DRP[121] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 10 | PLL[0]: DRP[121] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 12 | PLL[0]: DRP[121] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[121] bit 14 | PLL[0]: DRP[121] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 0 | PLL[0]: DRP[122] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 2 | PLL[0]: DRP[122] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 4 | PLL[0]: DRP[122] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 6 | PLL[0]: DRP[122] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 8 | PLL[0]: DRP[122] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 10 | PLL[0]: DRP[122] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 12 | PLL[0]: DRP[122] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[122] bit 14 | PLL[0]: DRP[122] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 0 | PLL[0]: DRP[123] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 2 | PLL[0]: DRP[123] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 4 | PLL[0]: DRP[123] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 6 | PLL[0]: DRP[123] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 8 | PLL[0]: DRP[123] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 10 | PLL[0]: DRP[123] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 12 | PLL[0]: DRP[123] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[123] bit 14 | PLL[0]: DRP[123] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 0 | PLL[0]: DRP[124] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 2 | PLL[0]: DRP[124] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 4 | PLL[0]: DRP[124] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 6 | PLL[0]: DRP[124] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 8 | PLL[0]: DRP[124] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 10 | PLL[0]: DRP[124] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 12 | PLL[0]: DRP[124] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[124] bit 14 | PLL[0]: DRP[124] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 0 | PLL[0]: DRP[125] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 2 | PLL[0]: DRP[125] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 4 | PLL[0]: DRP[125] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 6 | PLL[0]: DRP[125] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 8 | PLL[0]: DRP[125] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 10 | PLL[0]: DRP[125] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 12 | PLL[0]: DRP[125] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[125] bit 14 | PLL[0]: DRP[125] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 0 | PLL[0]: DRP[126] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 2 | PLL[0]: DRP[126] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 4 | PLL[0]: DRP[126] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 6 | PLL[0]: DRP[126] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 8 | PLL[0]: DRP[126] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 10 | PLL[0]: DRP[126] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 12 | PLL[0]: DRP[126] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[126] bit 14 | PLL[0]: DRP[126] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 0 | PLL[0]: DRP[127] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 2 | PLL[0]: DRP[127] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 4 | PLL[0]: DRP[127] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 6 | PLL[0]: DRP[127] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 8 | PLL[0]: DRP[127] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 10 | PLL[0]: DRP[127] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 12 | PLL[0]: DRP[127] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[127] bit 14 | PLL[0]: DRP[127] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 0 | PLL[0]: DRP[112] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 2 | PLL[0]: DRP[112] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 4 | PLL[0]: DRP[112] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 6 | PLL[0]: DRP[112] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 8 | PLL[0]: DRP[112] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 10 | PLL[0]: DRP[112] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 12 | PLL[0]: DRP[112] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[112] bit 14 | PLL[0]: DRP[112] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 0 | PLL[0]: DRP[113] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 2 | PLL[0]: DRP[113] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 4 | PLL[0]: DRP[113] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 6 | PLL[0]: DRP[113] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 8 | PLL[0]: DRP[113] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 10 | PLL[0]: DRP[113] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 12 | PLL[0]: DRP[113] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[113] bit 14 | PLL[0]: DRP[113] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: invert RST PLL[0]: DRP[114] bit 0 | PLL[0]: invert PWRDWN PLL[0]: DRP[114] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: invert PSINCDEC PLL[0]: DRP[114] bit 2 | PLL[0]: invert PSEN PLL[0]: DRP[114] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: invert CLKINSEL PLL[0]: DRP[114] bit 4 | PLL[0]: DRP[114] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[114] bit 6 | PLL[0]: DRP[114] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[114] bit 8 | PLL[0]: DRP[114] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[114] bit 10 | PLL[0]: DRP[114] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[114] bit 12 | PLL[0]: DRP[114] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[114] bit 14 | PLL[0]: DRP[114] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 0 | PLL[0]: DRP[115] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 2 | PLL[0]: DRP[115] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 4 | PLL[0]: DRP[115] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 6 | PLL[0]: DRP[115] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 8 | PLL[0]: DRP[115] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 10 | PLL[0]: DRP[115] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 12 | PLL[0]: DRP[115] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[115] bit 14 | PLL[0]: DRP[115] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 0 | PLL[0]: DRP[116] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 2 | PLL[0]: DRP[116] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 4 | PLL[0]: DRP[116] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 6 | PLL[0]: DRP[116] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 8 | PLL[0]: DRP[116] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 10 | PLL[0]: DRP[116] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 12 | PLL[0]: DRP[116] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[116] bit 14 | PLL[0]: DRP[116] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 0 | PLL[0]: DRP[117] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 2 | PLL[0]: DRP[117] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 4 | PLL[0]: DRP[117] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 6 | PLL[0]: DRP[117] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 8 | PLL[0]: DRP[117] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 10 | PLL[0]: DRP[117] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 12 | PLL[0]: DRP[117] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[117] bit 14 | PLL[0]: DRP[117] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 0 | PLL[0]: DRP[118] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 2 | PLL[0]: DRP[118] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 4 | PLL[0]: DRP[118] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 6 | PLL[0]: DRP[118] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 8 | PLL[0]: DRP[118] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 10 | PLL[0]: DRP[118] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 12 | PLL[0]: DRP[118] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[118] bit 14 | PLL[0]: DRP[118] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 0 | PLL[0]: DRP[119] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 2 | PLL[0]: DRP[119] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 4 | PLL[0]: DRP[119] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 6 | PLL[0]: DRP[119] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 8 | PLL[0]: DRP[119] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 10 | PLL[0]: DRP[119] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 12 | PLL[0]: DRP[119] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[119] bit 14 | PLL[0]: DRP[119] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 0 | PLL[0]: DRP[104] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 2 | PLL[0]: DRP[104] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 4 | PLL[0]: DRP[104] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 6 | PLL[0]: DRP[104] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 8 | PLL[0]: DRP[104] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 10 | PLL[0]: DRP[104] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 12 | PLL[0]: DRP[104] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[104] bit 14 | PLL[0]: DRP[104] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 0 | PLL[0]: DRP[105] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 2 | PLL[0]: DRP[105] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 4 | PLL[0]: DRP[105] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 6 | PLL[0]: DRP[105] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 8 | PLL[0]: DRP[105] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 10 | PLL[0]: DRP[105] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 12 | PLL[0]: DRP[105] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[105] bit 14 | PLL[0]: DRP[105] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 0 | PLL[0]: DRP[106] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 2 | PLL[0]: DRP[106] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 4 | PLL[0]: DRP[106] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 6 | PLL[0]: DRP[106] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 8 | PLL[0]: DRP[106] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 10 | PLL[0]: DRP[106] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 12 | PLL[0]: DRP[106] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[106] bit 14 | PLL[0]: DRP[106] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 0 | PLL[0]: DRP[107] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 2 | PLL[0]: DRP[107] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 4 | PLL[0]: DRP[107] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 6 | PLL[0]: DRP[107] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 8 | PLL[0]: DRP[107] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 10 | PLL[0]: DRP[107] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 12 | PLL[0]: DRP[107] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[107] bit 14 | PLL[0]: DRP[107] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 0 | PLL[0]: DRP[108] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 2 | PLL[0]: DRP[108] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 4 | PLL[0]: DRP[108] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 6 | PLL[0]: DRP[108] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 8 | PLL[0]: DRP[108] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 10 | PLL[0]: DRP[108] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 12 | PLL[0]: DRP[108] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[108] bit 14 | PLL[0]: DRP[108] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 0 | PLL[0]: DRP[109] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 2 | PLL[0]: DRP[109] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 4 | PLL[0]: DRP[109] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 6 | PLL[0]: DRP[109] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 8 | PLL[0]: DRP[109] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 10 | PLL[0]: DRP[109] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 12 | PLL[0]: DRP[109] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[109] bit 14 | PLL[0]: DRP[109] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 0 | PLL[0]: DRP[110] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 2 | PLL[0]: DRP[110] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 4 | PLL[0]: DRP[110] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 6 | PLL[0]: DRP[110] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 8 | PLL[0]: DRP[110] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 10 | PLL[0]: DRP[110] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 12 | PLL[0]: DRP[110] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[110] bit 14 | PLL[0]: DRP[110] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 0 | PLL[0]: DRP[111] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 2 | PLL[0]: DRP[111] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 4 | PLL[0]: DRP[111] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 6 | PLL[0]: DRP[111] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 8 | PLL[0]: DRP[111] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 10 | PLL[0]: DRP[111] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 12 | PLL[0]: DRP[111] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[111] bit 14 | PLL[0]: DRP[111] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 0 | PLL[0]: DRP[96] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 2 | PLL[0]: DRP[96] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 4 | PLL[0]: DRP[96] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 6 | PLL[0]: DRP[96] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 8 | PLL[0]: DRP[96] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 10 | PLL[0]: DRP[96] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 12 | PLL[0]: DRP[96] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[96] bit 14 | PLL[0]: DRP[96] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 0 | PLL[0]: DRP[97] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 2 | PLL[0]: DRP[97] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 4 | PLL[0]: DRP[97] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 6 | PLL[0]: DRP[97] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 8 | PLL[0]: DRP[97] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 10 | PLL[0]: DRP[97] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 12 | PLL[0]: DRP[97] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[97] bit 14 | PLL[0]: DRP[97] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 0 | PLL[0]: DRP[98] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 2 | PLL[0]: DRP[98] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 4 | PLL[0]: DRP[98] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 6 | PLL[0]: DRP[98] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 8 | PLL[0]: DRP[98] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 10 | PLL[0]: DRP[98] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 12 | PLL[0]: DRP[98] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[98] bit 14 | PLL[0]: DRP[98] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 0 | PLL[0]: DRP[99] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 2 | PLL[0]: DRP[99] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 4 | PLL[0]: DRP[99] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 6 | PLL[0]: DRP[99] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 8 | PLL[0]: DRP[99] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 10 | PLL[0]: DRP[99] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 12 | PLL[0]: DRP[99] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[99] bit 14 | PLL[0]: DRP[99] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 0 | PLL[0]: DRP[100] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 2 | PLL[0]: DRP[100] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 4 | PLL[0]: DRP[100] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 6 | PLL[0]: DRP[100] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 8 | PLL[0]: DRP[100] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 10 | PLL[0]: DRP[100] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 12 | PLL[0]: DRP[100] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[100] bit 14 | PLL[0]: DRP[100] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 0 | PLL[0]: DRP[101] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 2 | PLL[0]: DRP[101] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 4 | PLL[0]: DRP[101] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 6 | PLL[0]: DRP[101] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 8 | PLL[0]: DRP[101] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 10 | PLL[0]: DRP[101] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 12 | PLL[0]: DRP[101] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[101] bit 14 | PLL[0]: DRP[101] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 0 | PLL[0]: DRP[102] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 2 | PLL[0]: DRP[102] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 4 | PLL[0]: DRP[102] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 6 | PLL[0]: DRP[102] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 8 | PLL[0]: DRP[102] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 10 | PLL[0]: DRP[102] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 12 | PLL[0]: DRP[102] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[102] bit 14 | PLL[0]: DRP[102] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 0 | PLL[0]: DRP[103] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 2 | PLL[0]: DRP[103] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 4 | PLL[0]: DRP[103] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 6 | PLL[0]: DRP[103] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 8 | PLL[0]: DRP[103] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 10 | PLL[0]: DRP[103] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 12 | PLL[0]: DRP[103] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[103] bit 14 | PLL[0]: DRP[103] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 0 | PLL[0]: DRP[88] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 2 | PLL[0]: DRP[88] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 4 | PLL[0]: DRP[88] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 6 | PLL[0]: DRP[88] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 8 | PLL[0]: DRP[88] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 10 | PLL[0]: DRP[88] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 12 | PLL[0]: DRP[88] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[88] bit 14 | PLL[0]: DRP[88] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 0 | PLL[0]: DRP[89] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 2 | PLL[0]: DRP[89] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 4 | PLL[0]: DRP[89] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 6 | PLL[0]: DRP[89] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 8 | PLL[0]: DRP[89] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 10 | PLL[0]: DRP[89] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 12 | PLL[0]: DRP[89] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[89] bit 14 | PLL[0]: DRP[89] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 0 | PLL[0]: DRP[90] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 2 | PLL[0]: DRP[90] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 4 | PLL[0]: DRP[90] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 6 | PLL[0]: DRP[90] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 8 | PLL[0]: DRP[90] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 10 | PLL[0]: DRP[90] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 12 | PLL[0]: DRP[90] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[90] bit 14 | PLL[0]: DRP[90] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 0 | PLL[0]: DRP[91] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 2 | PLL[0]: DRP[91] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 4 | PLL[0]: DRP[91] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 6 | PLL[0]: DRP[91] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 8 | PLL[0]: DRP[91] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 10 | PLL[0]: DRP[91] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 12 | PLL[0]: DRP[91] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[91] bit 14 | PLL[0]: DRP[91] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 0 | PLL[0]: DRP[92] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 2 | PLL[0]: DRP[92] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 4 | PLL[0]: DRP[92] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 6 | PLL[0]: DRP[92] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 8 | PLL[0]: DRP[92] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 10 | PLL[0]: DRP[92] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 12 | PLL[0]: DRP[92] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[92] bit 14 | PLL[0]: DRP[92] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 0 | PLL[0]: DRP[93] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 2 | PLL[0]: DRP[93] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 4 | PLL[0]: DRP[93] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 6 | PLL[0]: DRP[93] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 8 | PLL[0]: DRP[93] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 10 | PLL[0]: DRP[93] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 12 | PLL[0]: DRP[93] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[93] bit 14 | PLL[0]: DRP[93] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 0 | PLL[0]: DRP[94] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 2 | PLL[0]: DRP[94] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 4 | PLL[0]: DRP[94] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 6 | PLL[0]: DRP[94] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 8 | PLL[0]: DRP[94] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 10 | PLL[0]: DRP[94] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 12 | PLL[0]: DRP[94] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[94] bit 14 | PLL[0]: DRP[94] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 0 | PLL[0]: DRP[95] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 2 | PLL[0]: DRP[95] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 4 | PLL[0]: DRP[95] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 6 | PLL[0]: DRP[95] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 8 | PLL[0]: DRP[95] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 10 | PLL[0]: DRP[95] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 12 | PLL[0]: DRP[95] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[95] bit 14 | PLL[0]: DRP[95] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 0 | PLL[0]: DRP[80] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 2 | PLL[0]: DRP[80] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 4 | PLL[0]: DRP[80] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 6 | PLL[0]: DRP[80] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 8 | PLL[0]: DRP[80] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 10 | PLL[0]: DRP[80] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 12 | PLL[0]: DRP[80] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[80] bit 14 | PLL[0]: DRP[80] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 0 | PLL[0]: DRP[81] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 2 | PLL[0]: DRP[81] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 4 | PLL[0]: DRP[81] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 6 | PLL[0]: DRP[81] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 8 | PLL[0]: DRP[81] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 10 | PLL[0]: DRP[81] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 12 | PLL[0]: DRP[81] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[81] bit 14 | PLL[0]: DRP[81] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 0 | PLL[0]: DRP[82] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 2 | PLL[0]: DRP[82] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 4 | PLL[0]: DRP[82] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 6 | PLL[0]: DRP[82] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 8 | PLL[0]: DRP[82] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 10 | PLL[0]: DRP[82] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 12 | PLL[0]: DRP[82] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[82] bit 14 | PLL[0]: DRP[82] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 0 | PLL[0]: DRP[83] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 2 | PLL[0]: DRP[83] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 4 | PLL[0]: DRP[83] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 6 | PLL[0]: DRP[83] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 8 | PLL[0]: DRP[83] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 10 | PLL[0]: DRP[83] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 12 | PLL[0]: DRP[83] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[83] bit 14 | PLL[0]: DRP[83] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 0 | PLL[0]: DRP[84] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 2 | PLL[0]: DRP[84] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 4 | PLL[0]: DRP[84] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 6 | PLL[0]: DRP[84] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 8 | PLL[0]: DRP[84] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 10 | PLL[0]: DRP[84] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 12 | PLL[0]: DRP[84] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[84] bit 14 | PLL[0]: DRP[84] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 0 | PLL[0]: DRP[85] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 2 | PLL[0]: DRP[85] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 4 | PLL[0]: DRP[85] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 6 | PLL[0]: DRP[85] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 8 | PLL[0]: DRP[85] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 10 | PLL[0]: DRP[85] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 12 | PLL[0]: DRP[85] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[85] bit 14 | PLL[0]: DRP[85] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 0 | PLL[0]: DRP[86] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 2 | PLL[0]: DRP[86] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 4 | PLL[0]: DRP[86] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 6 | PLL[0]: DRP[86] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 8 | PLL[0]: DRP[86] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 10 | PLL[0]: DRP[86] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 12 | PLL[0]: DRP[86] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[86] bit 14 | PLL[0]: DRP[86] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 0 | PLL[0]: DRP[87] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 2 | PLL[0]: DRP[87] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 4 | PLL[0]: DRP[87] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 6 | PLL[0]: DRP[87] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 8 | PLL[0]: DRP[87] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 10 | PLL[0]: DRP[87] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 12 | PLL[0]: DRP[87] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[87] bit 14 | PLL[0]: DRP[87] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 0 | PLL[0]: DRP[72] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 2 | PLL[0]: DRP[72] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 4 | PLL[0]: DRP[72] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 6 | PLL[0]: DRP[72] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 8 | PLL[0]: DRP[72] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 10 | PLL[0]: DRP[72] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 12 | PLL[0]: DRP[72] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[72] bit 14 | PLL[0]: DRP[72] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 0 | PLL[0]: DRP[73] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 2 | PLL[0]: DRP[73] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 4 | PLL[0]: DRP[73] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 6 | PLL[0]: DRP[73] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 8 | PLL[0]: DRP[73] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 10 | PLL[0]: DRP[73] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 12 | PLL[0]: DRP[73] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[73] bit 14 | PLL[0]: DRP[73] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 0 | PLL[0]: DRP[74] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 2 | PLL[0]: DRP[74] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 4 | PLL[0]: DRP[74] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 6 | PLL[0]: DRP[74] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 8 | PLL[0]: DRP[74] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 10 | PLL[0]: DRP[74] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 12 | PLL[0]: DRP[74] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[74] bit 14 | PLL[0]: DRP[74] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 0 | PLL[0]: DRP[75] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 2 | PLL[0]: DRP[75] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 4 | PLL[0]: DRP[75] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 6 | PLL[0]: DRP[75] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 8 | PLL[0]: DRP[75] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 10 | PLL[0]: DRP[75] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 12 | PLL[0]: DRP[75] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[75] bit 14 | PLL[0]: DRP[75] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 0 | PLL[0]: DRP[76] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 2 | PLL[0]: DRP[76] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 4 | PLL[0]: DRP[76] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 6 | PLL[0]: DRP[76] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 8 | PLL[0]: DRP[76] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 10 | PLL[0]: DRP[76] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 12 | PLL[0]: DRP[76] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[76] bit 14 | PLL[0]: DRP[76] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 0 | PLL[0]: DRP[77] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 2 | PLL[0]: DRP[77] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 4 | PLL[0]: DRP[77] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 6 | PLL[0]: DRP[77] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 8 | PLL[0]: DRP[77] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 10 | PLL[0]: DRP[77] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 12 | PLL[0]: DRP[77] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[77] bit 14 | PLL[0]: DRP[77] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 0 | PLL[0]: DRP[78] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 2 | PLL[0]: DRP[78] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 4 | PLL[0]: DRP[78] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 6 | PLL[0]: DRP[78] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 8 | PLL[0]: DRP[78] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 10 | PLL[0]: DRP[78] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 12 | PLL[0]: DRP[78] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[78] bit 14 | PLL[0]: DRP[78] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 0 | PLL[0]: DRP[79] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 2 | PLL[0]: DRP[79] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 4 | PLL[0]: DRP[79] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 6 | PLL[0]: DRP[79] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 8 | PLL[0]: DRP[79] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 10 | PLL[0]: DRP[79] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 12 | PLL[0]: DRP[79] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[79] bit 14 | PLL[0]: DRP[79] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 0 | PLL[0]: DRP[64] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 2 | PLL[0]: DRP[64] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 4 | PLL[0]: DRP[64] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 6 | PLL[0]: DRP[64] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 8 | PLL[0]: DRP[64] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 10 | PLL[0]: DRP[64] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 12 | PLL[0]: DRP[64] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[64] bit 14 | PLL[0]: DRP[64] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 0 | PLL[0]: DRP[65] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 2 | PLL[0]: DRP[65] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 4 | PLL[0]: DRP[65] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 6 | PLL[0]: DRP[65] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 8 | PLL[0]: DRP[65] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 10 | PLL[0]: DRP[65] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 12 | PLL[0]: DRP[65] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[65] bit 14 | PLL[0]: DRP[65] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 0 | PLL[0]: DRP[66] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 2 | PLL[0]: DRP[66] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 4 | PLL[0]: DRP[66] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 6 | PLL[0]: DRP[66] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 8 | PLL[0]: DRP[66] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 10 | PLL[0]: DRP[66] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 12 | PLL[0]: DRP[66] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[66] bit 14 | PLL[0]: DRP[66] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 0 | PLL[0]: DRP[67] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 2 | PLL[0]: DRP[67] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 4 | PLL[0]: DRP[67] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 6 | PLL[0]: DRP[67] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 8 | PLL[0]: DRP[67] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 10 | PLL[0]: DRP[67] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 12 | PLL[0]: DRP[67] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[67] bit 14 | PLL[0]: DRP[67] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 0 | PLL[0]: DRP[68] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 2 | PLL[0]: DRP[68] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 4 | PLL[0]: DRP[68] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 6 | PLL[0]: DRP[68] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 8 | PLL[0]: DRP[68] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 10 | PLL[0]: DRP[68] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 12 | PLL[0]: DRP[68] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[68] bit 14 | PLL[0]: DRP[68] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 0 | PLL[0]: DRP[69] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 2 | PLL[0]: DRP[69] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 4 | PLL[0]: DRP[69] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 6 | PLL[0]: DRP[69] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 8 | PLL[0]: DRP[69] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 10 | PLL[0]: DRP[69] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 12 | PLL[0]: DRP[69] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[69] bit 14 | PLL[0]: DRP[69] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 0 | PLL[0]: DRP[70] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 2 | PLL[0]: DRP[70] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 4 | PLL[0]: DRP[70] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 6 | PLL[0]: DRP[70] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 8 | PLL[0]: DRP[70] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 10 | PLL[0]: DRP[70] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 12 | PLL[0]: DRP[70] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[70] bit 14 | PLL[0]: DRP[70] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 0 | PLL[0]: DRP[71] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 2 | PLL[0]: DRP[71] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 4 | PLL[0]: DRP[71] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 6 | PLL[0]: DRP[71] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 8 | PLL[0]: DRP[71] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 10 | PLL[0]: DRP[71] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 12 | PLL[0]: DRP[71] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[71] bit 14 | PLL[0]: DRP[71] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 0 | PLL[0]: DRP[56] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 2 | PLL[0]: DRP[56] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 4 | PLL[0]: DRP[56] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 6 | PLL[0]: DRP[56] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 8 | PLL[0]: DRP[56] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 10 | PLL[0]: DRP[56] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 12 | PLL[0]: DRP[56] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[56] bit 14 | PLL[0]: DRP[56] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 0 | PLL[0]: DRP[57] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 2 | PLL[0]: DRP[57] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 4 | PLL[0]: DRP[57] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 6 | PLL[0]: DRP[57] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 8 | PLL[0]: DRP[57] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 10 | PLL[0]: DRP[57] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 12 | PLL[0]: DRP[57] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[57] bit 14 | PLL[0]: DRP[57] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 0 | PLL[0]: DRP[58] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 2 | PLL[0]: DRP[58] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 4 | PLL[0]: DRP[58] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 6 | PLL[0]: DRP[58] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 8 | PLL[0]: DRP[58] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 10 | PLL[0]: DRP[58] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 12 | PLL[0]: DRP[58] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[58] bit 14 | PLL[0]: DRP[58] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 0 | PLL[0]: DRP[59] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 2 | PLL[0]: DRP[59] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 4 | PLL[0]: DRP[59] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 6 | PLL[0]: DRP[59] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 8 | PLL[0]: DRP[59] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 10 | PLL[0]: DRP[59] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 12 | PLL[0]: DRP[59] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[59] bit 14 | PLL[0]: DRP[59] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 0 | PLL[0]: DRP[60] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 2 | PLL[0]: DRP[60] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 4 | PLL[0]: DRP[60] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 6 | PLL[0]: DRP[60] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 8 | PLL[0]: DRP[60] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 10 | PLL[0]: DRP[60] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 12 | PLL[0]: DRP[60] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[60] bit 14 | PLL[0]: DRP[60] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 0 | PLL[0]: DRP[61] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 2 | PLL[0]: DRP[61] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 4 | PLL[0]: DRP[61] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 6 | PLL[0]: DRP[61] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 8 | PLL[0]: DRP[61] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 10 | PLL[0]: DRP[61] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 12 | PLL[0]: DRP[61] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[61] bit 14 | PLL[0]: DRP[61] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 0 | PLL[0]: DRP[62] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 2 | PLL[0]: DRP[62] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 4 | PLL[0]: DRP[62] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 6 | PLL[0]: DRP[62] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 8 | PLL[0]: DRP[62] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 10 | PLL[0]: DRP[62] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 12 | PLL[0]: DRP[62] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[62] bit 14 | PLL[0]: DRP[62] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 0 | PLL[0]: DRP[63] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 2 | PLL[0]: DRP[63] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 4 | PLL[0]: DRP[63] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 6 | PLL[0]: DRP[63] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 8 | PLL[0]: DRP[63] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 10 | PLL[0]: DRP[63] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 12 | PLL[0]: DRP[63] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[63] bit 14 | PLL[0]: DRP[63] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 0 | PLL[0]: DRP[48] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 2 | PLL[0]: DRP[48] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 4 | PLL[0]: DRP[48] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 6 | PLL[0]: DRP[48] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 8 | PLL[0]: DRP[48] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 10 | PLL[0]: DRP[48] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 12 | PLL[0]: DRP[48] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[48] bit 14 | PLL[0]: DRP[48] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 0 | PLL[0]: DRP[49] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 2 | PLL[0]: DRP[49] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 4 | PLL[0]: DRP[49] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 6 | PLL[0]: DRP[49] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 8 | PLL[0]: DRP[49] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 10 | PLL[0]: DRP[49] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 12 | PLL[0]: DRP[49] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[49] bit 14 | PLL[0]: DRP[49] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 0 | PLL[0]: DRP[50] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 2 | PLL[0]: DRP[50] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 4 | PLL[0]: DRP[50] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 6 | PLL[0]: DRP[50] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 8 | PLL[0]: DRP[50] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 10 | PLL[0]: DRP[50] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 12 | PLL[0]: DRP[50] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[50] bit 14 | PLL[0]: DRP[50] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 0 | PLL[0]: DRP[51] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 2 | PLL[0]: DRP[51] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 4 | PLL[0]: DRP[51] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 6 | PLL[0]: DRP[51] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 8 | PLL[0]: DRP[51] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 10 | PLL[0]: DRP[51] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 12 | PLL[0]: DRP[51] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[51] bit 14 | PLL[0]: DRP[51] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 0 | PLL[0]: DRP[52] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 2 | PLL[0]: DRP[52] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 4 | PLL[0]: DRP[52] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 6 | PLL[0]: DRP[52] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 8 | PLL[0]: DRP[52] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 10 | PLL[0]: DRP[52] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 12 | PLL[0]: DRP[52] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[52] bit 14 | PLL[0]: DRP[52] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 0 | PLL[0]: DRP[53] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 2 | PLL[0]: DRP[53] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 4 | PLL[0]: DRP[53] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 6 | PLL[0]: DRP[53] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 8 | PLL[0]: DRP[53] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 10 | PLL[0]: DRP[53] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 12 | PLL[0]: DRP[53] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[53] bit 14 | PLL[0]: DRP[53] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 0 | PLL[0]: DRP[54] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 2 | PLL[0]: DRP[54] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 4 | PLL[0]: DRP[54] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 6 | PLL[0]: DRP[54] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 8 | PLL[0]: DRP[54] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 10 | PLL[0]: DRP[54] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 12 | PLL[0]: DRP[54] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[54] bit 14 | PLL[0]: DRP[54] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 0 | PLL[0]: DRP[55] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 2 | PLL[0]: DRP[55] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 4 | PLL[0]: DRP[55] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 6 | PLL[0]: DRP[55] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 8 | PLL[0]: DRP[55] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 10 | PLL[0]: DRP[55] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 12 | PLL[0]: DRP[55] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[55] bit 14 | PLL[0]: DRP[55] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 0 | PLL[0]: DRP[40] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 2 | PLL[0]: DRP[40] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 4 | PLL[0]: DRP[40] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 6 | PLL[0]: DRP[40] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 8 | PLL[0]: DRP[40] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 10 | PLL[0]: DRP[40] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 12 | PLL[0]: DRP[40] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[40] bit 14 | PLL[0]: DRP[40] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 0 | PLL[0]: DRP[41] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 2 | PLL[0]: DRP[41] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 4 | PLL[0]: DRP[41] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 6 | PLL[0]: DRP[41] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 8 | PLL[0]: DRP[41] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 10 | PLL[0]: DRP[41] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 12 | PLL[0]: DRP[41] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[41] bit 14 | PLL[0]: DRP[41] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 0 | PLL[0]: DRP[42] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 2 | PLL[0]: DRP[42] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 4 | PLL[0]: DRP[42] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 6 | PLL[0]: DRP[42] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 8 | PLL[0]: DRP[42] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 10 | PLL[0]: DRP[42] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 12 | PLL[0]: DRP[42] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[42] bit 14 | PLL[0]: DRP[42] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 0 | PLL[0]: DRP[43] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 2 | PLL[0]: DRP[43] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 4 | PLL[0]: DRP[43] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 6 | PLL[0]: DRP[43] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 8 | PLL[0]: DRP[43] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 10 | PLL[0]: DRP[43] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 12 | PLL[0]: DRP[43] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[43] bit 14 | PLL[0]: DRP[43] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 0 | PLL[0]: DRP[44] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 2 | PLL[0]: DRP[44] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 4 | PLL[0]: DRP[44] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 6 | PLL[0]: DRP[44] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 8 | PLL[0]: DRP[44] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 10 | PLL[0]: DRP[44] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 12 | PLL[0]: DRP[44] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[44] bit 14 | PLL[0]: DRP[44] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 0 | PLL[0]: DRP[45] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 2 | PLL[0]: DRP[45] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 4 | PLL[0]: DRP[45] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 6 | PLL[0]: DRP[45] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 8 | PLL[0]: DRP[45] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 10 | PLL[0]: DRP[45] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 12 | PLL[0]: DRP[45] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[45] bit 14 | PLL[0]: DRP[45] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 0 | PLL[0]: DRP[46] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 2 | PLL[0]: DRP[46] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 4 | PLL[0]: DRP[46] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 6 | PLL[0]: DRP[46] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 8 | PLL[0]: DRP[46] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 10 | PLL[0]: DRP[46] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 12 | PLL[0]: DRP[46] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[46] bit 14 | PLL[0]: DRP[46] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 0 | PLL[0]: DRP[47] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 2 | PLL[0]: DRP[47] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 4 | PLL[0]: DRP[47] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 6 | PLL[0]: DRP[47] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 8 | PLL[0]: DRP[47] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 10 | PLL[0]: DRP[47] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 12 | PLL[0]: DRP[47] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[47] bit 14 | PLL[0]: DRP[47] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 0 | PLL[0]: DRP[32] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 2 | PLL[0]: DRP[32] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 4 | PLL[0]: DRP[32] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 6 | PLL[0]: DRP[32] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 8 | PLL[0]: DRP[32] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 10 | PLL[0]: DRP[32] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 12 | PLL[0]: DRP[32] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[32] bit 14 | PLL[0]: DRP[32] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 0 | PLL[0]: DRP[33] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 2 | PLL[0]: DRP[33] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 4 | PLL[0]: DRP[33] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 6 | PLL[0]: DRP[33] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 8 | PLL[0]: DRP[33] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 10 | PLL[0]: DRP[33] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 12 | PLL[0]: DRP[33] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[33] bit 14 | PLL[0]: DRP[33] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 0 | PLL[0]: DRP[34] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 2 | PLL[0]: DRP[34] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 4 | PLL[0]: DRP[34] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 6 | PLL[0]: DRP[34] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 8 | PLL[0]: DRP[34] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 10 | PLL[0]: DRP[34] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 12 | PLL[0]: DRP[34] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[34] bit 14 | PLL[0]: DRP[34] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 0 | PLL[0]: DRP[35] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 2 | PLL[0]: DRP[35] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 4 | PLL[0]: DRP[35] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 6 | PLL[0]: DRP[35] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 8 | PLL[0]: DRP[35] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 10 | PLL[0]: DRP[35] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 12 | PLL[0]: DRP[35] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[35] bit 14 | PLL[0]: DRP[35] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 0 | PLL[0]: DRP[36] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 2 | PLL[0]: DRP[36] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 4 | PLL[0]: DRP[36] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 6 | PLL[0]: DRP[36] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 8 | PLL[0]: DRP[36] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 10 | PLL[0]: DRP[36] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 12 | PLL[0]: DRP[36] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[36] bit 14 | PLL[0]: DRP[36] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 0 | PLL[0]: DRP[37] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 2 | PLL[0]: DRP[37] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 4 | PLL[0]: DRP[37] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 6 | PLL[0]: DRP[37] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 8 | PLL[0]: DRP[37] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 10 | PLL[0]: DRP[37] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 12 | PLL[0]: DRP[37] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[37] bit 14 | PLL[0]: DRP[37] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 0 | PLL[0]: DRP[38] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 2 | PLL[0]: DRP[38] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 4 | PLL[0]: DRP[38] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 6 | PLL[0]: DRP[38] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 8 | PLL[0]: DRP[38] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 10 | PLL[0]: DRP[38] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 12 | PLL[0]: DRP[38] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[38] bit 14 | PLL[0]: DRP[38] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 0 | PLL[0]: DRP[39] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 2 | PLL[0]: DRP[39] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 4 | PLL[0]: DRP[39] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 6 | PLL[0]: DRP[39] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 8 | PLL[0]: DRP[39] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 10 | PLL[0]: DRP[39] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 12 | PLL[0]: DRP[39] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[39] bit 14 | PLL[0]: DRP[39] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 0 | PLL[0]: DRP[24] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 2 | PLL[0]: DRP[24] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 4 | PLL[0]: DRP[24] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 6 | PLL[0]: DRP[24] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 8 | PLL[0]: DRP[24] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 10 | PLL[0]: DRP[24] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 12 | PLL[0]: DRP[24] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[24] bit 14 | PLL[0]: DRP[24] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 0 | PLL[0]: DRP[25] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 2 | PLL[0]: DRP[25] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 4 | PLL[0]: DRP[25] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 6 | PLL[0]: DRP[25] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 8 | PLL[0]: DRP[25] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 10 | PLL[0]: DRP[25] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 12 | PLL[0]: DRP[25] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[25] bit 14 | PLL[0]: DRP[25] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 0 | PLL[0]: DRP[26] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 2 | PLL[0]: DRP[26] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 4 | PLL[0]: DRP[26] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 6 | PLL[0]: DRP[26] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 8 | PLL[0]: DRP[26] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 10 | PLL[0]: DRP[26] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 12 | PLL[0]: DRP[26] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[26] bit 14 | PLL[0]: DRP[26] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 0 | PLL[0]: DRP[27] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 2 | PLL[0]: DRP[27] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 4 | PLL[0]: DRP[27] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 6 | PLL[0]: DRP[27] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 8 | PLL[0]: DRP[27] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 10 | PLL[0]: DRP[27] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 12 | PLL[0]: DRP[27] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[27] bit 14 | PLL[0]: DRP[27] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 0 | PLL[0]: DRP[28] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 2 | PLL[0]: DRP[28] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 4 | PLL[0]: DRP[28] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 6 | PLL[0]: DRP[28] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 8 | PLL[0]: DRP[28] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 10 | PLL[0]: DRP[28] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 12 | PLL[0]: DRP[28] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[28] bit 14 | PLL[0]: DRP[28] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 0 | PLL[0]: DRP[29] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 2 | PLL[0]: DRP[29] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 4 | PLL[0]: DRP[29] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 6 | PLL[0]: DRP[29] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 8 | PLL[0]: DRP[29] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 10 | PLL[0]: DRP[29] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 12 | PLL[0]: DRP[29] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[29] bit 14 | PLL[0]: DRP[29] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 0 | PLL[0]: DRP[30] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 2 | PLL[0]: DRP[30] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 4 | PLL[0]: DRP[30] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 6 | PLL[0]: DRP[30] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 8 | PLL[0]: DRP[30] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 10 | PLL[0]: DRP[30] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 12 | PLL[0]: DRP[30] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[30] bit 14 | PLL[0]: DRP[30] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 0 | PLL[0]: DRP[31] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 2 | PLL[0]: DRP[31] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 4 | PLL[0]: DRP[31] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 6 | PLL[0]: DRP[31] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 8 | PLL[0]: DRP[31] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 10 | PLL[0]: DRP[31] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 12 | PLL[0]: DRP[31] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[31] bit 14 | PLL[0]: DRP[31] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 0 | PLL[0]: DRP[16] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 2 | PLL[0]: DRP[16] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 4 | PLL[0]: DRP[16] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 6 | PLL[0]: DRP[16] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 8 | PLL[0]: DRP[16] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 10 | PLL[0]: DRP[16] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 12 | PLL[0]: DRP[16] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[16] bit 14 | PLL[0]: DRP[16] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 0 | PLL[0]: DRP[17] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 2 | PLL[0]: DRP[17] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 4 | PLL[0]: DRP[17] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 6 | PLL[0]: DRP[17] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 8 | PLL[0]: DRP[17] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 10 | PLL[0]: DRP[17] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 12 | PLL[0]: DRP[17] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[17] bit 14 | PLL[0]: DRP[17] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 0 | PLL[0]: DRP[18] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 2 | PLL[0]: DRP[18] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 4 | PLL[0]: DRP[18] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 6 | PLL[0]: DRP[18] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 8 | PLL[0]: DRP[18] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 10 | PLL[0]: DRP[18] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 12 | PLL[0]: DRP[18] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[18] bit 14 | PLL[0]: DRP[18] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 0 | PLL[0]: DRP[19] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 2 | PLL[0]: DRP[19] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 4 | PLL[0]: DRP[19] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 6 | PLL[0]: DRP[19] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 8 | PLL[0]: DRP[19] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 10 | PLL[0]: DRP[19] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 12 | PLL[0]: DRP[19] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[19] bit 14 | PLL[0]: DRP[19] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 0 | PLL[0]: DRP[20] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 2 | PLL[0]: DRP[20] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 4 | PLL[0]: DRP[20] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 6 | PLL[0]: DRP[20] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 8 | PLL[0]: DRP[20] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 10 | PLL[0]: DRP[20] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 12 | PLL[0]: DRP[20] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[20] bit 14 | PLL[0]: DRP[20] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 0 | PLL[0]: DRP[21] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 2 | PLL[0]: DRP[21] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 4 | PLL[0]: DRP[21] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 6 | PLL[0]: DRP[21] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 8 | PLL[0]: DRP[21] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 10 | PLL[0]: DRP[21] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 12 | PLL[0]: DRP[21] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[21] bit 14 | PLL[0]: DRP[21] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 0 | PLL[0]: DRP[22] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 2 | PLL[0]: DRP[22] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 4 | PLL[0]: DRP[22] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 6 | PLL[0]: DRP[22] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 8 | PLL[0]: DRP[22] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 10 | PLL[0]: DRP[22] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 12 | PLL[0]: DRP[22] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[22] bit 14 | PLL[0]: DRP[22] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 0 | PLL[0]: DRP[23] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 2 | PLL[0]: DRP[23] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 4 | PLL[0]: DRP[23] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 6 | PLL[0]: DRP[23] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 8 | PLL[0]: DRP[23] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 10 | PLL[0]: DRP[23] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 12 | PLL[0]: DRP[23] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[23] bit 14 | PLL[0]: DRP[23] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 0 | PLL[0]: DRP[8] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 2 | PLL[0]: DRP[8] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 4 | PLL[0]: DRP[8] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 6 | PLL[0]: DRP[8] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 8 | PLL[0]: DRP[8] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 10 | PLL[0]: DRP[8] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 12 | PLL[0]: DRP[8] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[8] bit 14 | PLL[0]: DRP[8] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 0 | PLL[0]: DRP[9] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 2 | PLL[0]: DRP[9] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 4 | PLL[0]: DRP[9] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 6 | PLL[0]: DRP[9] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 8 | PLL[0]: DRP[9] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 10 | PLL[0]: DRP[9] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 12 | PLL[0]: DRP[9] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[9] bit 14 | PLL[0]: DRP[9] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 0 | PLL[0]: DRP[10] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 2 | PLL[0]: DRP[10] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 4 | PLL[0]: DRP[10] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 6 | PLL[0]: DRP[10] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 8 | PLL[0]: DRP[10] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 10 | PLL[0]: DRP[10] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 12 | PLL[0]: DRP[10] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[10] bit 14 | PLL[0]: DRP[10] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 0 | PLL[0]: DRP[11] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 2 | PLL[0]: DRP[11] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 4 | PLL[0]: DRP[11] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 6 | PLL[0]: DRP[11] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 8 | PLL[0]: DRP[11] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 10 | PLL[0]: DRP[11] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 12 | PLL[0]: DRP[11] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[11] bit 14 | PLL[0]: DRP[11] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 0 | PLL[0]: DRP[12] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 2 | PLL[0]: DRP[12] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 4 | PLL[0]: DRP[12] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 6 | PLL[0]: DRP[12] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 8 | PLL[0]: DRP[12] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 10 | PLL[0]: DRP[12] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 12 | PLL[0]: DRP[12] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[12] bit 14 | PLL[0]: DRP[12] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 0 | PLL[0]: DRP[13] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 2 | PLL[0]: DRP[13] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 4 | PLL[0]: DRP[13] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 6 | PLL[0]: DRP[13] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 8 | PLL[0]: DRP[13] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 10 | PLL[0]: DRP[13] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 12 | PLL[0]: DRP[13] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[13] bit 14 | PLL[0]: DRP[13] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 0 | PLL[0]: DRP[14] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 2 | PLL[0]: DRP[14] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 4 | PLL[0]: DRP[14] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 6 | PLL[0]: DRP[14] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 8 | PLL[0]: DRP[14] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 10 | PLL[0]: DRP[14] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 12 | PLL[0]: DRP[14] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[14] bit 14 | PLL[0]: DRP[14] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 0 | PLL[0]: DRP[15] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 2 | PLL[0]: DRP[15] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 4 | PLL[0]: DRP[15] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 6 | PLL[0]: DRP[15] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 8 | PLL[0]: DRP[15] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 10 | PLL[0]: DRP[15] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 12 | PLL[0]: DRP[15] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[15] bit 14 | PLL[0]: DRP[15] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[0] bit 0 PLL[0]: DRP[0] bit 0 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[0] bit 1 PLL[0]: DRP[0] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[0] bit 0 PLL[0]: DRP[0] bit 2 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[0] bit 1 PLL[0]: DRP[0] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[0] bit 0 PLL[0]: DRP[0] bit 4 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[0] bit 1 PLL[0]: DRP[0] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[0] bit 6 | PLL[0]: DRP[0] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[0] bit 8 | PLL[0]: DRP[0] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[0] bit 10 | PLL[0]: DRP[0] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[0] bit 12 | PLL[0]: DRP[0] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[0] bit 14 | PLL[0]: DRP[0] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: DRP[1] bit 0 | SPEC_INT: buffer IO_E[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: DRP[1] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: DRP[1] bit 2 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: DRP[1] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: DRP[1] bit 4 | SPEC_INT: buffer IO_E[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: DRP[1] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: DRP[1] bit 6 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: DRP[1] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: DRP[1] bit 8 | SPEC_INT: buffer IO_E[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: DRP[1] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: DRP[1] bit 10 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: DRP[1] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: DRP[1] bit 12 | SPEC_INT: buffer IO_E[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: DRP[1] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: DRP[1] bit 14 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: DRP[1] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 0 | PLL[0]: DRP[2] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 2 | PLL[0]: DRP[2] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 4 | PLL[0]: DRP[2] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 6 | PLL[0]: DRP[2] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 8 | PLL[0]: DRP[2] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 10 | PLL[0]: DRP[2] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 12 | PLL[0]: DRP[2] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[2] bit 14 | PLL[0]: DRP[2] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 0 | PLL[0]: DRP[3] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 2 | PLL[0]: DRP[3] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 4 | PLL[0]: DRP[3] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 6 | PLL[0]: DRP[3] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 8 | PLL[0]: DRP[3] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[3] bit 10 | PLL[0]: DRP[3] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 0 PLL[0]: DRP[3] bit 12 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 0 PLL[0]: DRP[3] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 0 PLL[0]: DRP[3] bit 14 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 0 PLL[0]: DRP[3] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 1 PLL[0]: DRP[4] bit 0 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 2 PLL[0]: DRP[4] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 1 PLL[0]: DRP[4] bit 2 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 2 PLL[0]: DRP[4] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 1 PLL[0]: DRP[4] bit 4 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 2 PLL[0]: DRP[4] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 1 PLL[0]: DRP[4] bit 6 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 2 PLL[0]: DRP[4] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[4] bit 8 | PLL[0]: DRP[4] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[4] bit 10 | PLL[0]: DRP[4] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[4] bit 12 | PLL[0]: DRP[4] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[4] bit 14 | PLL[0]: DRP[4] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 0 PLL[0]: DRP[5] bit 0 | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 1 PLL[0]: DRP[5] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 2 PLL[0]: DRP[5] bit 2 | PLL[0]: DRP[5] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 4 | PLL[0]: DRP[5] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 6 | PLL[0]: DRP[5] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 8 | PLL[0]: DRP[5] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 10 | PLL[0]: DRP[5] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 12 | PLL[0]: DRP[5] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[5] bit 14 | PLL[0]: DRP[5] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 0 | PLL[0]: DRP[6] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 2 | PLL[0]: DRP[6] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 4 | PLL[0]: DRP[6] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 6 | PLL[0]: DRP[6] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 8 | PLL[0]: DRP[6] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 10 | PLL[0]: DRP[6] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 12 | PLL[0]: DRP[6] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[6] bit 14 | PLL[0]: DRP[6] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 0 | PLL[0]: DRP[7] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 2 | PLL[0]: DRP[7] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 4 | PLL[0]: DRP[7] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 6 | PLL[0]: DRP[7] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 8 | PLL[0]: DRP[7] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 10 | PLL[0]: DRP[7] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 12 | PLL[0]: DRP[7] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]: DRP[7] bit 14 | PLL[0]: DRP[7] bit 15 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 14 | PLL[1]: DRP[7] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 12 | PLL[1]: DRP[7] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 10 | PLL[1]: DRP[7] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 8 | PLL[1]: DRP[7] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 6 | PLL[1]: DRP[7] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 4 | PLL[1]: DRP[7] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 2 | PLL[1]: DRP[7] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[7] bit 0 | PLL[1]: DRP[7] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 14 | PLL[1]: DRP[6] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 12 | PLL[1]: DRP[6] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 10 | PLL[1]: DRP[6] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 8 | PLL[1]: DRP[6] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 6 | PLL[1]: DRP[6] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 4 | PLL[1]: DRP[6] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 2 | PLL[1]: DRP[6] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[6] bit 0 | PLL[1]: DRP[6] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 14 | PLL[1]: DRP[5] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 12 | PLL[1]: DRP[5] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 10 | PLL[1]: DRP[5] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 8 | PLL[1]: DRP[5] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 6 | PLL[1]: DRP[5] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[5] bit 4 | PLL[1]: DRP[5] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 2 PLL[1]: DRP[5] bit 2 | PLL[1]: DRP[5] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 0 PLL[1]: DRP[5] bit 0 | SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 1 PLL[1]: DRP[5] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[4] bit 14 | PLL[1]: DRP[4] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[4] bit 12 | PLL[1]: DRP[4] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[4] bit 10 | PLL[1]: DRP[4] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[4] bit 8 | PLL[1]: DRP[4] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 1 PLL[1]: DRP[4] bit 6 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 2 PLL[1]: DRP[4] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 1 PLL[1]: DRP[4] bit 4 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 2 PLL[1]: DRP[4] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 1 PLL[1]: DRP[4] bit 2 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 2 PLL[1]: DRP[4] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 1 PLL[1]: DRP[4] bit 0 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 2 PLL[1]: DRP[4] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 0 PLL[1]: DRP[3] bit 14 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 0 PLL[1]: DRP[3] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 0 PLL[1]: DRP[3] bit 12 | SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 0 PLL[1]: DRP[3] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 10 | PLL[1]: DRP[3] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 8 | PLL[1]: DRP[3] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 6 | PLL[1]: DRP[3] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 4 | PLL[1]: DRP[3] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 2 | PLL[1]: DRP[3] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[3] bit 0 | PLL[1]: DRP[3] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 14 | PLL[1]: DRP[2] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 12 | PLL[1]: DRP[2] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 10 | PLL[1]: DRP[2] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 8 | PLL[1]: DRP[2] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 6 | PLL[1]: DRP[2] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 4 | PLL[1]: DRP[2] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 2 | PLL[1]: DRP[2] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[2] bit 0 | PLL[1]: DRP[2] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: DRP[1] bit 14 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: DRP[1] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: DRP[1] bit 12 | SPEC_INT: buffer IO_E[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: DRP[1] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: DRP[1] bit 10 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: DRP[1] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: DRP[1] bit 8 | SPEC_INT: buffer IO_E[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: DRP[1] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: DRP[1] bit 6 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: DRP[1] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: DRP[1] bit 4 | SPEC_INT: buffer IO_E[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: DRP[1] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_W[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: DRP[1] bit 2 | SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: DRP[1] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: DRP[1] bit 0 | SPEC_INT: buffer IO_E[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: DRP[1] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[0] bit 14 | PLL[1]: DRP[0] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[0] bit 12 | PLL[1]: DRP[0] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[0] bit 10 | PLL[1]: DRP[0] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[0] bit 8 | PLL[1]: DRP[0] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[0] bit 6 | PLL[1]: DRP[0] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[1] bit 0 PLL[1]: DRP[0] bit 4 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[1] bit 1 PLL[1]: DRP[0] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[1] bit 0 PLL[1]: DRP[0] bit 2 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[1] bit 1 PLL[1]: DRP[0] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[1] bit 0 PLL[1]: DRP[0] bit 0 | SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[1] bit 1 PLL[1]: DRP[0] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 14 | PLL[1]: DRP[15] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 12 | PLL[1]: DRP[15] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 10 | PLL[1]: DRP[15] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 8 | PLL[1]: DRP[15] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 6 | PLL[1]: DRP[15] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 4 | PLL[1]: DRP[15] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 2 | PLL[1]: DRP[15] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[15] bit 0 | PLL[1]: DRP[15] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 14 | PLL[1]: DRP[14] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 12 | PLL[1]: DRP[14] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 10 | PLL[1]: DRP[14] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 8 | PLL[1]: DRP[14] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 6 | PLL[1]: DRP[14] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 4 | PLL[1]: DRP[14] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 2 | PLL[1]: DRP[14] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[14] bit 0 | PLL[1]: DRP[14] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 14 | PLL[1]: DRP[13] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 12 | PLL[1]: DRP[13] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 10 | PLL[1]: DRP[13] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 8 | PLL[1]: DRP[13] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 6 | PLL[1]: DRP[13] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 4 | PLL[1]: DRP[13] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 2 | PLL[1]: DRP[13] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[13] bit 0 | PLL[1]: DRP[13] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 14 | PLL[1]: DRP[12] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 12 | PLL[1]: DRP[12] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 10 | PLL[1]: DRP[12] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 8 | PLL[1]: DRP[12] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 6 | PLL[1]: DRP[12] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 4 | PLL[1]: DRP[12] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 2 | PLL[1]: DRP[12] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[12] bit 0 | PLL[1]: DRP[12] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 14 | PLL[1]: DRP[11] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 12 | PLL[1]: DRP[11] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 10 | PLL[1]: DRP[11] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 8 | PLL[1]: DRP[11] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 6 | PLL[1]: DRP[11] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 4 | PLL[1]: DRP[11] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 2 | PLL[1]: DRP[11] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[11] bit 0 | PLL[1]: DRP[11] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 14 | PLL[1]: DRP[10] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 12 | PLL[1]: DRP[10] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 10 | PLL[1]: DRP[10] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 8 | PLL[1]: DRP[10] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 6 | PLL[1]: DRP[10] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 4 | PLL[1]: DRP[10] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 2 | PLL[1]: DRP[10] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[10] bit 0 | PLL[1]: DRP[10] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 14 | PLL[1]: DRP[9] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 12 | PLL[1]: DRP[9] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 10 | PLL[1]: DRP[9] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 8 | PLL[1]: DRP[9] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 6 | PLL[1]: DRP[9] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 4 | PLL[1]: DRP[9] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 2 | PLL[1]: DRP[9] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[9] bit 0 | PLL[1]: DRP[9] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 14 | PLL[1]: DRP[8] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 12 | PLL[1]: DRP[8] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 10 | PLL[1]: DRP[8] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 8 | PLL[1]: DRP[8] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 6 | PLL[1]: DRP[8] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 4 | PLL[1]: DRP[8] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 2 | PLL[1]: DRP[8] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[8] bit 0 | PLL[1]: DRP[8] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 14 | PLL[1]: DRP[23] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 12 | PLL[1]: DRP[23] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 10 | PLL[1]: DRP[23] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 8 | PLL[1]: DRP[23] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 6 | PLL[1]: DRP[23] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 4 | PLL[1]: DRP[23] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 2 | PLL[1]: DRP[23] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[23] bit 0 | PLL[1]: DRP[23] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 14 | PLL[1]: DRP[22] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 12 | PLL[1]: DRP[22] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 10 | PLL[1]: DRP[22] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 8 | PLL[1]: DRP[22] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 6 | PLL[1]: DRP[22] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 4 | PLL[1]: DRP[22] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 2 | PLL[1]: DRP[22] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[22] bit 0 | PLL[1]: DRP[22] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 14 | PLL[1]: DRP[21] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 12 | PLL[1]: DRP[21] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 10 | PLL[1]: DRP[21] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 8 | PLL[1]: DRP[21] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 6 | PLL[1]: DRP[21] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 4 | PLL[1]: DRP[21] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 2 | PLL[1]: DRP[21] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[21] bit 0 | PLL[1]: DRP[21] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 14 | PLL[1]: DRP[20] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 12 | PLL[1]: DRP[20] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 10 | PLL[1]: DRP[20] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 8 | PLL[1]: DRP[20] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 6 | PLL[1]: DRP[20] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 4 | PLL[1]: DRP[20] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 2 | PLL[1]: DRP[20] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[20] bit 0 | PLL[1]: DRP[20] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 14 | PLL[1]: DRP[19] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 12 | PLL[1]: DRP[19] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 10 | PLL[1]: DRP[19] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 8 | PLL[1]: DRP[19] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 6 | PLL[1]: DRP[19] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 4 | PLL[1]: DRP[19] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 2 | PLL[1]: DRP[19] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[19] bit 0 | PLL[1]: DRP[19] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 14 | PLL[1]: DRP[18] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 12 | PLL[1]: DRP[18] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 10 | PLL[1]: DRP[18] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 8 | PLL[1]: DRP[18] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 6 | PLL[1]: DRP[18] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 4 | PLL[1]: DRP[18] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 2 | PLL[1]: DRP[18] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[18] bit 0 | PLL[1]: DRP[18] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 14 | PLL[1]: DRP[17] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 12 | PLL[1]: DRP[17] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 10 | PLL[1]: DRP[17] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 8 | PLL[1]: DRP[17] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 6 | PLL[1]: DRP[17] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 4 | PLL[1]: DRP[17] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 2 | PLL[1]: DRP[17] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[17] bit 0 | PLL[1]: DRP[17] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 14 | PLL[1]: DRP[16] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 12 | PLL[1]: DRP[16] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 10 | PLL[1]: DRP[16] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 8 | PLL[1]: DRP[16] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 6 | PLL[1]: DRP[16] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 4 | PLL[1]: DRP[16] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 2 | PLL[1]: DRP[16] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[16] bit 0 | PLL[1]: DRP[16] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 14 | PLL[1]: DRP[31] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 12 | PLL[1]: DRP[31] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 10 | PLL[1]: DRP[31] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 8 | PLL[1]: DRP[31] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 6 | PLL[1]: DRP[31] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 4 | PLL[1]: DRP[31] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 2 | PLL[1]: DRP[31] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[31] bit 0 | PLL[1]: DRP[31] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 14 | PLL[1]: DRP[30] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 12 | PLL[1]: DRP[30] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 10 | PLL[1]: DRP[30] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 8 | PLL[1]: DRP[30] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 6 | PLL[1]: DRP[30] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 4 | PLL[1]: DRP[30] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 2 | PLL[1]: DRP[30] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[30] bit 0 | PLL[1]: DRP[30] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 14 | PLL[1]: DRP[29] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 12 | PLL[1]: DRP[29] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 10 | PLL[1]: DRP[29] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 8 | PLL[1]: DRP[29] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 6 | PLL[1]: DRP[29] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 4 | PLL[1]: DRP[29] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 2 | PLL[1]: DRP[29] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[29] bit 0 | PLL[1]: DRP[29] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 14 | PLL[1]: DRP[28] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 12 | PLL[1]: DRP[28] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 10 | PLL[1]: DRP[28] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 8 | PLL[1]: DRP[28] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 6 | PLL[1]: DRP[28] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 4 | PLL[1]: DRP[28] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 2 | PLL[1]: DRP[28] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[28] bit 0 | PLL[1]: DRP[28] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 14 | PLL[1]: DRP[27] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 12 | PLL[1]: DRP[27] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 10 | PLL[1]: DRP[27] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 8 | PLL[1]: DRP[27] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 6 | PLL[1]: DRP[27] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 4 | PLL[1]: DRP[27] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 2 | PLL[1]: DRP[27] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[27] bit 0 | PLL[1]: DRP[27] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 14 | PLL[1]: DRP[26] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 12 | PLL[1]: DRP[26] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 10 | PLL[1]: DRP[26] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 8 | PLL[1]: DRP[26] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 6 | PLL[1]: DRP[26] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 4 | PLL[1]: DRP[26] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 2 | PLL[1]: DRP[26] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[26] bit 0 | PLL[1]: DRP[26] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 14 | PLL[1]: DRP[25] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 12 | PLL[1]: DRP[25] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 10 | PLL[1]: DRP[25] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 8 | PLL[1]: DRP[25] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 6 | PLL[1]: DRP[25] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 4 | PLL[1]: DRP[25] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 2 | PLL[1]: DRP[25] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[25] bit 0 | PLL[1]: DRP[25] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 14 | PLL[1]: DRP[24] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 12 | PLL[1]: DRP[24] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 10 | PLL[1]: DRP[24] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 8 | PLL[1]: DRP[24] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 6 | PLL[1]: DRP[24] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 4 | PLL[1]: DRP[24] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 2 | PLL[1]: DRP[24] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[24] bit 0 | PLL[1]: DRP[24] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 14 | PLL[1]: DRP[39] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 12 | PLL[1]: DRP[39] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 10 | PLL[1]: DRP[39] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 8 | PLL[1]: DRP[39] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 6 | PLL[1]: DRP[39] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 4 | PLL[1]: DRP[39] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 2 | PLL[1]: DRP[39] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[39] bit 0 | PLL[1]: DRP[39] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 14 | PLL[1]: DRP[38] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 12 | PLL[1]: DRP[38] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 10 | PLL[1]: DRP[38] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 8 | PLL[1]: DRP[38] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 6 | PLL[1]: DRP[38] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 4 | PLL[1]: DRP[38] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 2 | PLL[1]: DRP[38] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[38] bit 0 | PLL[1]: DRP[38] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 14 | PLL[1]: DRP[37] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 12 | PLL[1]: DRP[37] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 10 | PLL[1]: DRP[37] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 8 | PLL[1]: DRP[37] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 6 | PLL[1]: DRP[37] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 4 | PLL[1]: DRP[37] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 2 | PLL[1]: DRP[37] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[37] bit 0 | PLL[1]: DRP[37] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 14 | PLL[1]: DRP[36] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 12 | PLL[1]: DRP[36] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 10 | PLL[1]: DRP[36] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 8 | PLL[1]: DRP[36] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 6 | PLL[1]: DRP[36] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 4 | PLL[1]: DRP[36] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 2 | PLL[1]: DRP[36] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[36] bit 0 | PLL[1]: DRP[36] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 14 | PLL[1]: DRP[35] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 12 | PLL[1]: DRP[35] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 10 | PLL[1]: DRP[35] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 8 | PLL[1]: DRP[35] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 6 | PLL[1]: DRP[35] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 4 | PLL[1]: DRP[35] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 2 | PLL[1]: DRP[35] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[35] bit 0 | PLL[1]: DRP[35] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 14 | PLL[1]: DRP[34] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 12 | PLL[1]: DRP[34] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 10 | PLL[1]: DRP[34] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 8 | PLL[1]: DRP[34] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 6 | PLL[1]: DRP[34] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 4 | PLL[1]: DRP[34] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 2 | PLL[1]: DRP[34] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[34] bit 0 | PLL[1]: DRP[34] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 14 | PLL[1]: DRP[33] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 12 | PLL[1]: DRP[33] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 10 | PLL[1]: DRP[33] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 8 | PLL[1]: DRP[33] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 6 | PLL[1]: DRP[33] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 4 | PLL[1]: DRP[33] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 2 | PLL[1]: DRP[33] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[33] bit 0 | PLL[1]: DRP[33] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 14 | PLL[1]: DRP[32] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 12 | PLL[1]: DRP[32] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 10 | PLL[1]: DRP[32] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 8 | PLL[1]: DRP[32] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 6 | PLL[1]: DRP[32] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 4 | PLL[1]: DRP[32] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 2 | PLL[1]: DRP[32] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[32] bit 0 | PLL[1]: DRP[32] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 14 | PLL[1]: DRP[47] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 12 | PLL[1]: DRP[47] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 10 | PLL[1]: DRP[47] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 8 | PLL[1]: DRP[47] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 6 | PLL[1]: DRP[47] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 4 | PLL[1]: DRP[47] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 2 | PLL[1]: DRP[47] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[47] bit 0 | PLL[1]: DRP[47] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 14 | PLL[1]: DRP[46] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 12 | PLL[1]: DRP[46] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 10 | PLL[1]: DRP[46] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 8 | PLL[1]: DRP[46] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 6 | PLL[1]: DRP[46] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 4 | PLL[1]: DRP[46] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 2 | PLL[1]: DRP[46] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[46] bit 0 | PLL[1]: DRP[46] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 14 | PLL[1]: DRP[45] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 12 | PLL[1]: DRP[45] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 10 | PLL[1]: DRP[45] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 8 | PLL[1]: DRP[45] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 6 | PLL[1]: DRP[45] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 4 | PLL[1]: DRP[45] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 2 | PLL[1]: DRP[45] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[45] bit 0 | PLL[1]: DRP[45] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 14 | PLL[1]: DRP[44] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 12 | PLL[1]: DRP[44] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 10 | PLL[1]: DRP[44] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 8 | PLL[1]: DRP[44] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 6 | PLL[1]: DRP[44] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 4 | PLL[1]: DRP[44] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 2 | PLL[1]: DRP[44] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[44] bit 0 | PLL[1]: DRP[44] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 14 | PLL[1]: DRP[43] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 12 | PLL[1]: DRP[43] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 10 | PLL[1]: DRP[43] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 8 | PLL[1]: DRP[43] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 6 | PLL[1]: DRP[43] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 4 | PLL[1]: DRP[43] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 2 | PLL[1]: DRP[43] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[43] bit 0 | PLL[1]: DRP[43] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 14 | PLL[1]: DRP[42] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 12 | PLL[1]: DRP[42] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 10 | PLL[1]: DRP[42] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 8 | PLL[1]: DRP[42] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 6 | PLL[1]: DRP[42] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 4 | PLL[1]: DRP[42] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 2 | PLL[1]: DRP[42] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[42] bit 0 | PLL[1]: DRP[42] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 14 | PLL[1]: DRP[41] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 12 | PLL[1]: DRP[41] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 10 | PLL[1]: DRP[41] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 8 | PLL[1]: DRP[41] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 6 | PLL[1]: DRP[41] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 4 | PLL[1]: DRP[41] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 2 | PLL[1]: DRP[41] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[41] bit 0 | PLL[1]: DRP[41] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 14 | PLL[1]: DRP[40] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 12 | PLL[1]: DRP[40] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 10 | PLL[1]: DRP[40] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 8 | PLL[1]: DRP[40] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 6 | PLL[1]: DRP[40] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 4 | PLL[1]: DRP[40] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 2 | PLL[1]: DRP[40] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[40] bit 0 | PLL[1]: DRP[40] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 14 | PLL[1]: DRP[55] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 12 | PLL[1]: DRP[55] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 10 | PLL[1]: DRP[55] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 8 | PLL[1]: DRP[55] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 6 | PLL[1]: DRP[55] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 4 | PLL[1]: DRP[55] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 2 | PLL[1]: DRP[55] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[55] bit 0 | PLL[1]: DRP[55] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 14 | PLL[1]: DRP[54] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 12 | PLL[1]: DRP[54] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 10 | PLL[1]: DRP[54] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 8 | PLL[1]: DRP[54] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 6 | PLL[1]: DRP[54] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 4 | PLL[1]: DRP[54] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 2 | PLL[1]: DRP[54] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[54] bit 0 | PLL[1]: DRP[54] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 14 | PLL[1]: DRP[53] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 12 | PLL[1]: DRP[53] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 10 | PLL[1]: DRP[53] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 8 | PLL[1]: DRP[53] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 6 | PLL[1]: DRP[53] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 4 | PLL[1]: DRP[53] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 2 | PLL[1]: DRP[53] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[53] bit 0 | PLL[1]: DRP[53] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 14 | PLL[1]: DRP[52] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 12 | PLL[1]: DRP[52] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 10 | PLL[1]: DRP[52] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 8 | PLL[1]: DRP[52] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 6 | PLL[1]: DRP[52] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 4 | PLL[1]: DRP[52] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 2 | PLL[1]: DRP[52] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[52] bit 0 | PLL[1]: DRP[52] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 14 | PLL[1]: DRP[51] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 12 | PLL[1]: DRP[51] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 10 | PLL[1]: DRP[51] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 8 | PLL[1]: DRP[51] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 6 | PLL[1]: DRP[51] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 4 | PLL[1]: DRP[51] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 2 | PLL[1]: DRP[51] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[51] bit 0 | PLL[1]: DRP[51] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 14 | PLL[1]: DRP[50] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 12 | PLL[1]: DRP[50] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 10 | PLL[1]: DRP[50] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 8 | PLL[1]: DRP[50] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 6 | PLL[1]: DRP[50] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 4 | PLL[1]: DRP[50] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 2 | PLL[1]: DRP[50] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[50] bit 0 | PLL[1]: DRP[50] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 14 | PLL[1]: DRP[49] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 12 | PLL[1]: DRP[49] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 10 | PLL[1]: DRP[49] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 8 | PLL[1]: DRP[49] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 6 | PLL[1]: DRP[49] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 4 | PLL[1]: DRP[49] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 2 | PLL[1]: DRP[49] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[49] bit 0 | PLL[1]: DRP[49] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 14 | PLL[1]: DRP[48] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 12 | PLL[1]: DRP[48] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 10 | PLL[1]: DRP[48] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 8 | PLL[1]: DRP[48] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 6 | PLL[1]: DRP[48] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 4 | PLL[1]: DRP[48] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 2 | PLL[1]: DRP[48] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[48] bit 0 | PLL[1]: DRP[48] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 14 | PLL[1]: DRP[63] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 12 | PLL[1]: DRP[63] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 10 | PLL[1]: DRP[63] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 8 | PLL[1]: DRP[63] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 6 | PLL[1]: DRP[63] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 4 | PLL[1]: DRP[63] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 2 | PLL[1]: DRP[63] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[63] bit 0 | PLL[1]: DRP[63] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 14 | PLL[1]: DRP[62] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 12 | PLL[1]: DRP[62] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 10 | PLL[1]: DRP[62] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 8 | PLL[1]: DRP[62] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 6 | PLL[1]: DRP[62] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 4 | PLL[1]: DRP[62] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 2 | PLL[1]: DRP[62] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[62] bit 0 | PLL[1]: DRP[62] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 14 | PLL[1]: DRP[61] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 12 | PLL[1]: DRP[61] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 10 | PLL[1]: DRP[61] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 8 | PLL[1]: DRP[61] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 6 | PLL[1]: DRP[61] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 4 | PLL[1]: DRP[61] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 2 | PLL[1]: DRP[61] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[61] bit 0 | PLL[1]: DRP[61] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 14 | PLL[1]: DRP[60] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 12 | PLL[1]: DRP[60] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 10 | PLL[1]: DRP[60] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 8 | PLL[1]: DRP[60] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 6 | PLL[1]: DRP[60] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 4 | PLL[1]: DRP[60] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 2 | PLL[1]: DRP[60] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[60] bit 0 | PLL[1]: DRP[60] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 14 | PLL[1]: DRP[59] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 12 | PLL[1]: DRP[59] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 10 | PLL[1]: DRP[59] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 8 | PLL[1]: DRP[59] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 6 | PLL[1]: DRP[59] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 4 | PLL[1]: DRP[59] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 2 | PLL[1]: DRP[59] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[59] bit 0 | PLL[1]: DRP[59] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 14 | PLL[1]: DRP[58] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 12 | PLL[1]: DRP[58] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 10 | PLL[1]: DRP[58] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 8 | PLL[1]: DRP[58] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 6 | PLL[1]: DRP[58] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 4 | PLL[1]: DRP[58] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 2 | PLL[1]: DRP[58] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[58] bit 0 | PLL[1]: DRP[58] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 14 | PLL[1]: DRP[57] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 12 | PLL[1]: DRP[57] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 10 | PLL[1]: DRP[57] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 8 | PLL[1]: DRP[57] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 6 | PLL[1]: DRP[57] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 4 | PLL[1]: DRP[57] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 2 | PLL[1]: DRP[57] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[57] bit 0 | PLL[1]: DRP[57] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 14 | PLL[1]: DRP[56] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 12 | PLL[1]: DRP[56] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 10 | PLL[1]: DRP[56] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 8 | PLL[1]: DRP[56] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 6 | PLL[1]: DRP[56] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 4 | PLL[1]: DRP[56] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 2 | PLL[1]: DRP[56] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[56] bit 0 | PLL[1]: DRP[56] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 14 | PLL[1]: DRP[71] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 12 | PLL[1]: DRP[71] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 10 | PLL[1]: DRP[71] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 8 | PLL[1]: DRP[71] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 6 | PLL[1]: DRP[71] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 4 | PLL[1]: DRP[71] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 2 | PLL[1]: DRP[71] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[71] bit 0 | PLL[1]: DRP[71] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 14 | PLL[1]: DRP[70] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 12 | PLL[1]: DRP[70] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 10 | PLL[1]: DRP[70] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 8 | PLL[1]: DRP[70] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 6 | PLL[1]: DRP[70] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 4 | PLL[1]: DRP[70] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 2 | PLL[1]: DRP[70] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[70] bit 0 | PLL[1]: DRP[70] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 14 | PLL[1]: DRP[69] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 12 | PLL[1]: DRP[69] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 10 | PLL[1]: DRP[69] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 8 | PLL[1]: DRP[69] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 6 | PLL[1]: DRP[69] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 4 | PLL[1]: DRP[69] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 2 | PLL[1]: DRP[69] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[69] bit 0 | PLL[1]: DRP[69] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 14 | PLL[1]: DRP[68] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 12 | PLL[1]: DRP[68] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 10 | PLL[1]: DRP[68] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 8 | PLL[1]: DRP[68] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 6 | PLL[1]: DRP[68] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 4 | PLL[1]: DRP[68] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 2 | PLL[1]: DRP[68] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[68] bit 0 | PLL[1]: DRP[68] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 14 | PLL[1]: DRP[67] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 12 | PLL[1]: DRP[67] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 10 | PLL[1]: DRP[67] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 8 | PLL[1]: DRP[67] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 6 | PLL[1]: DRP[67] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 4 | PLL[1]: DRP[67] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 2 | PLL[1]: DRP[67] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[67] bit 0 | PLL[1]: DRP[67] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 14 | PLL[1]: DRP[66] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 12 | PLL[1]: DRP[66] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 10 | PLL[1]: DRP[66] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 8 | PLL[1]: DRP[66] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 6 | PLL[1]: DRP[66] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 4 | PLL[1]: DRP[66] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 2 | PLL[1]: DRP[66] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[66] bit 0 | PLL[1]: DRP[66] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 14 | PLL[1]: DRP[65] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 12 | PLL[1]: DRP[65] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 10 | PLL[1]: DRP[65] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 8 | PLL[1]: DRP[65] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 6 | PLL[1]: DRP[65] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 4 | PLL[1]: DRP[65] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 2 | PLL[1]: DRP[65] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[65] bit 0 | PLL[1]: DRP[65] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 14 | PLL[1]: DRP[64] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 12 | PLL[1]: DRP[64] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 10 | PLL[1]: DRP[64] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 8 | PLL[1]: DRP[64] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 6 | PLL[1]: DRP[64] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 4 | PLL[1]: DRP[64] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 2 | PLL[1]: DRP[64] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[64] bit 0 | PLL[1]: DRP[64] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 14 | PLL[1]: DRP[79] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 12 | PLL[1]: DRP[79] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 10 | PLL[1]: DRP[79] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 8 | PLL[1]: DRP[79] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 6 | PLL[1]: DRP[79] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 4 | PLL[1]: DRP[79] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 2 | PLL[1]: DRP[79] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[79] bit 0 | PLL[1]: DRP[79] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 14 | PLL[1]: DRP[78] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 12 | PLL[1]: DRP[78] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 10 | PLL[1]: DRP[78] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 8 | PLL[1]: DRP[78] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 6 | PLL[1]: DRP[78] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 4 | PLL[1]: DRP[78] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 2 | PLL[1]: DRP[78] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[78] bit 0 | PLL[1]: DRP[78] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 14 | PLL[1]: DRP[77] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 12 | PLL[1]: DRP[77] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 10 | PLL[1]: DRP[77] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 8 | PLL[1]: DRP[77] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 6 | PLL[1]: DRP[77] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 4 | PLL[1]: DRP[77] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 2 | PLL[1]: DRP[77] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[77] bit 0 | PLL[1]: DRP[77] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 14 | PLL[1]: DRP[76] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 12 | PLL[1]: DRP[76] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 10 | PLL[1]: DRP[76] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 8 | PLL[1]: DRP[76] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 6 | PLL[1]: DRP[76] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 4 | PLL[1]: DRP[76] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 2 | PLL[1]: DRP[76] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[76] bit 0 | PLL[1]: DRP[76] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 14 | PLL[1]: DRP[75] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 12 | PLL[1]: DRP[75] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 10 | PLL[1]: DRP[75] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 8 | PLL[1]: DRP[75] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 6 | PLL[1]: DRP[75] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 4 | PLL[1]: DRP[75] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 2 | PLL[1]: DRP[75] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[75] bit 0 | PLL[1]: DRP[75] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 14 | PLL[1]: DRP[74] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 12 | PLL[1]: DRP[74] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 10 | PLL[1]: DRP[74] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 8 | PLL[1]: DRP[74] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 6 | PLL[1]: DRP[74] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 4 | PLL[1]: DRP[74] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 2 | PLL[1]: DRP[74] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[74] bit 0 | PLL[1]: DRP[74] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 14 | PLL[1]: DRP[73] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 12 | PLL[1]: DRP[73] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 10 | PLL[1]: DRP[73] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 8 | PLL[1]: DRP[73] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 6 | PLL[1]: DRP[73] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 4 | PLL[1]: DRP[73] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 2 | PLL[1]: DRP[73] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[73] bit 0 | PLL[1]: DRP[73] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 14 | PLL[1]: DRP[72] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 12 | PLL[1]: DRP[72] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 10 | PLL[1]: DRP[72] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 8 | PLL[1]: DRP[72] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 6 | PLL[1]: DRP[72] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 4 | PLL[1]: DRP[72] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 2 | PLL[1]: DRP[72] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[72] bit 0 | PLL[1]: DRP[72] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 14 | PLL[1]: DRP[87] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 12 | PLL[1]: DRP[87] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 10 | PLL[1]: DRP[87] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 8 | PLL[1]: DRP[87] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 6 | PLL[1]: DRP[87] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 4 | PLL[1]: DRP[87] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 2 | PLL[1]: DRP[87] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[87] bit 0 | PLL[1]: DRP[87] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 14 | PLL[1]: DRP[86] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 12 | PLL[1]: DRP[86] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 10 | PLL[1]: DRP[86] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 8 | PLL[1]: DRP[86] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 6 | PLL[1]: DRP[86] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 4 | PLL[1]: DRP[86] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 2 | PLL[1]: DRP[86] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[86] bit 0 | PLL[1]: DRP[86] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 14 | PLL[1]: DRP[85] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 12 | PLL[1]: DRP[85] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 10 | PLL[1]: DRP[85] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 8 | PLL[1]: DRP[85] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 6 | PLL[1]: DRP[85] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 4 | PLL[1]: DRP[85] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 2 | PLL[1]: DRP[85] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[85] bit 0 | PLL[1]: DRP[85] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 14 | PLL[1]: DRP[84] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 12 | PLL[1]: DRP[84] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 10 | PLL[1]: DRP[84] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 8 | PLL[1]: DRP[84] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 6 | PLL[1]: DRP[84] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 4 | PLL[1]: DRP[84] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 2 | PLL[1]: DRP[84] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[84] bit 0 | PLL[1]: DRP[84] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 14 | PLL[1]: DRP[83] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 12 | PLL[1]: DRP[83] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 10 | PLL[1]: DRP[83] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 8 | PLL[1]: DRP[83] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 6 | PLL[1]: DRP[83] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 4 | PLL[1]: DRP[83] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 2 | PLL[1]: DRP[83] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[83] bit 0 | PLL[1]: DRP[83] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 14 | PLL[1]: DRP[82] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 12 | PLL[1]: DRP[82] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 10 | PLL[1]: DRP[82] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 8 | PLL[1]: DRP[82] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 6 | PLL[1]: DRP[82] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 4 | PLL[1]: DRP[82] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 2 | PLL[1]: DRP[82] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[82] bit 0 | PLL[1]: DRP[82] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 14 | PLL[1]: DRP[81] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 12 | PLL[1]: DRP[81] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 10 | PLL[1]: DRP[81] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 8 | PLL[1]: DRP[81] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 6 | PLL[1]: DRP[81] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 4 | PLL[1]: DRP[81] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 2 | PLL[1]: DRP[81] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[81] bit 0 | PLL[1]: DRP[81] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 14 | PLL[1]: DRP[80] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 12 | PLL[1]: DRP[80] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 10 | PLL[1]: DRP[80] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 8 | PLL[1]: DRP[80] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 6 | PLL[1]: DRP[80] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 4 | PLL[1]: DRP[80] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 2 | PLL[1]: DRP[80] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[80] bit 0 | PLL[1]: DRP[80] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 14 | PLL[1]: DRP[95] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 12 | PLL[1]: DRP[95] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 10 | PLL[1]: DRP[95] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 8 | PLL[1]: DRP[95] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 6 | PLL[1]: DRP[95] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 4 | PLL[1]: DRP[95] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 2 | PLL[1]: DRP[95] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[95] bit 0 | PLL[1]: DRP[95] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 14 | PLL[1]: DRP[94] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 12 | PLL[1]: DRP[94] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 10 | PLL[1]: DRP[94] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 8 | PLL[1]: DRP[94] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 6 | PLL[1]: DRP[94] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 4 | PLL[1]: DRP[94] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 2 | PLL[1]: DRP[94] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[94] bit 0 | PLL[1]: DRP[94] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 14 | PLL[1]: DRP[93] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 12 | PLL[1]: DRP[93] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 10 | PLL[1]: DRP[93] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 8 | PLL[1]: DRP[93] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 6 | PLL[1]: DRP[93] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 4 | PLL[1]: DRP[93] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 2 | PLL[1]: DRP[93] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[93] bit 0 | PLL[1]: DRP[93] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 14 | PLL[1]: DRP[92] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 12 | PLL[1]: DRP[92] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 10 | PLL[1]: DRP[92] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 8 | PLL[1]: DRP[92] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 6 | PLL[1]: DRP[92] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 4 | PLL[1]: DRP[92] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 2 | PLL[1]: DRP[92] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[92] bit 0 | PLL[1]: DRP[92] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 14 | PLL[1]: DRP[91] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 12 | PLL[1]: DRP[91] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 10 | PLL[1]: DRP[91] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 8 | PLL[1]: DRP[91] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 6 | PLL[1]: DRP[91] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 4 | PLL[1]: DRP[91] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 2 | PLL[1]: DRP[91] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[91] bit 0 | PLL[1]: DRP[91] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 14 | PLL[1]: DRP[90] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 12 | PLL[1]: DRP[90] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 10 | PLL[1]: DRP[90] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 8 | PLL[1]: DRP[90] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 6 | PLL[1]: DRP[90] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 4 | PLL[1]: DRP[90] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 2 | PLL[1]: DRP[90] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[90] bit 0 | PLL[1]: DRP[90] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 14 | PLL[1]: DRP[89] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 12 | PLL[1]: DRP[89] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 10 | PLL[1]: DRP[89] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 8 | PLL[1]: DRP[89] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 6 | PLL[1]: DRP[89] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 4 | PLL[1]: DRP[89] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 2 | PLL[1]: DRP[89] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[89] bit 0 | PLL[1]: DRP[89] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 14 | PLL[1]: DRP[88] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 12 | PLL[1]: DRP[88] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 10 | PLL[1]: DRP[88] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 8 | PLL[1]: DRP[88] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 6 | PLL[1]: DRP[88] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 4 | PLL[1]: DRP[88] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 2 | PLL[1]: DRP[88] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[88] bit 0 | PLL[1]: DRP[88] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 14 | PLL[1]: DRP[103] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 12 | PLL[1]: DRP[103] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 10 | PLL[1]: DRP[103] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 8 | PLL[1]: DRP[103] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 6 | PLL[1]: DRP[103] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 4 | PLL[1]: DRP[103] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 2 | PLL[1]: DRP[103] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[103] bit 0 | PLL[1]: DRP[103] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 14 | PLL[1]: DRP[102] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 12 | PLL[1]: DRP[102] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 10 | PLL[1]: DRP[102] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 8 | PLL[1]: DRP[102] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 6 | PLL[1]: DRP[102] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 4 | PLL[1]: DRP[102] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 2 | PLL[1]: DRP[102] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[102] bit 0 | PLL[1]: DRP[102] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 14 | PLL[1]: DRP[101] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 12 | PLL[1]: DRP[101] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 10 | PLL[1]: DRP[101] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 8 | PLL[1]: DRP[101] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 6 | PLL[1]: DRP[101] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 4 | PLL[1]: DRP[101] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 2 | PLL[1]: DRP[101] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[101] bit 0 | PLL[1]: DRP[101] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 14 | PLL[1]: DRP[100] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 12 | PLL[1]: DRP[100] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 10 | PLL[1]: DRP[100] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 8 | PLL[1]: DRP[100] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 6 | PLL[1]: DRP[100] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 4 | PLL[1]: DRP[100] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 2 | PLL[1]: DRP[100] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[100] bit 0 | PLL[1]: DRP[100] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 14 | PLL[1]: DRP[99] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 12 | PLL[1]: DRP[99] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 10 | PLL[1]: DRP[99] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 8 | PLL[1]: DRP[99] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 6 | PLL[1]: DRP[99] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 4 | PLL[1]: DRP[99] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 2 | PLL[1]: DRP[99] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[99] bit 0 | PLL[1]: DRP[99] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 14 | PLL[1]: DRP[98] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 12 | PLL[1]: DRP[98] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 10 | PLL[1]: DRP[98] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 8 | PLL[1]: DRP[98] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 6 | PLL[1]: DRP[98] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 4 | PLL[1]: DRP[98] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 2 | PLL[1]: DRP[98] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[98] bit 0 | PLL[1]: DRP[98] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 14 | PLL[1]: DRP[97] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 12 | PLL[1]: DRP[97] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 10 | PLL[1]: DRP[97] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 8 | PLL[1]: DRP[97] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 6 | PLL[1]: DRP[97] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 4 | PLL[1]: DRP[97] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 2 | PLL[1]: DRP[97] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[97] bit 0 | PLL[1]: DRP[97] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 14 | PLL[1]: DRP[96] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 12 | PLL[1]: DRP[96] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 10 | PLL[1]: DRP[96] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 8 | PLL[1]: DRP[96] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 6 | PLL[1]: DRP[96] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 4 | PLL[1]: DRP[96] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 2 | PLL[1]: DRP[96] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[96] bit 0 | PLL[1]: DRP[96] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 14 | PLL[1]: DRP[111] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 12 | PLL[1]: DRP[111] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 10 | PLL[1]: DRP[111] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 8 | PLL[1]: DRP[111] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 6 | PLL[1]: DRP[111] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 4 | PLL[1]: DRP[111] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 2 | PLL[1]: DRP[111] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[111] bit 0 | PLL[1]: DRP[111] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 14 | PLL[1]: DRP[110] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 12 | PLL[1]: DRP[110] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 10 | PLL[1]: DRP[110] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 8 | PLL[1]: DRP[110] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 6 | PLL[1]: DRP[110] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 4 | PLL[1]: DRP[110] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 2 | PLL[1]: DRP[110] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[110] bit 0 | PLL[1]: DRP[110] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 14 | PLL[1]: DRP[109] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 12 | PLL[1]: DRP[109] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 10 | PLL[1]: DRP[109] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 8 | PLL[1]: DRP[109] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 6 | PLL[1]: DRP[109] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 4 | PLL[1]: DRP[109] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 2 | PLL[1]: DRP[109] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[109] bit 0 | PLL[1]: DRP[109] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 14 | PLL[1]: DRP[108] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 12 | PLL[1]: DRP[108] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 10 | PLL[1]: DRP[108] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 8 | PLL[1]: DRP[108] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 6 | PLL[1]: DRP[108] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 4 | PLL[1]: DRP[108] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 2 | PLL[1]: DRP[108] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[108] bit 0 | PLL[1]: DRP[108] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 14 | PLL[1]: DRP[107] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 12 | PLL[1]: DRP[107] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 10 | PLL[1]: DRP[107] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 8 | PLL[1]: DRP[107] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 6 | PLL[1]: DRP[107] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 4 | PLL[1]: DRP[107] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 2 | PLL[1]: DRP[107] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[107] bit 0 | PLL[1]: DRP[107] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 14 | PLL[1]: DRP[106] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 12 | PLL[1]: DRP[106] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 10 | PLL[1]: DRP[106] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 8 | PLL[1]: DRP[106] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 6 | PLL[1]: DRP[106] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 4 | PLL[1]: DRP[106] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 2 | PLL[1]: DRP[106] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[106] bit 0 | PLL[1]: DRP[106] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 14 | PLL[1]: DRP[105] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 12 | PLL[1]: DRP[105] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 10 | PLL[1]: DRP[105] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 8 | PLL[1]: DRP[105] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 6 | PLL[1]: DRP[105] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 4 | PLL[1]: DRP[105] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 2 | PLL[1]: DRP[105] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[105] bit 0 | PLL[1]: DRP[105] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 14 | PLL[1]: DRP[104] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 12 | PLL[1]: DRP[104] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 10 | PLL[1]: DRP[104] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 8 | PLL[1]: DRP[104] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 6 | PLL[1]: DRP[104] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 4 | PLL[1]: DRP[104] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 2 | PLL[1]: DRP[104] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[104] bit 0 | PLL[1]: DRP[104] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 14 | PLL[1]: DRP[119] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 12 | PLL[1]: DRP[119] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 10 | PLL[1]: DRP[119] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 8 | PLL[1]: DRP[119] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 6 | PLL[1]: DRP[119] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 4 | PLL[1]: DRP[119] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 2 | PLL[1]: DRP[119] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[119] bit 0 | PLL[1]: DRP[119] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 14 | PLL[1]: DRP[118] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 12 | PLL[1]: DRP[118] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 10 | PLL[1]: DRP[118] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 8 | PLL[1]: DRP[118] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 6 | PLL[1]: DRP[118] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 4 | PLL[1]: DRP[118] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 2 | PLL[1]: DRP[118] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[118] bit 0 | PLL[1]: DRP[118] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 14 | PLL[1]: DRP[117] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 12 | PLL[1]: DRP[117] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 10 | PLL[1]: DRP[117] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 8 | PLL[1]: DRP[117] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 6 | PLL[1]: DRP[117] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 4 | PLL[1]: DRP[117] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 2 | PLL[1]: DRP[117] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[117] bit 0 | PLL[1]: DRP[117] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 14 | PLL[1]: DRP[116] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 12 | PLL[1]: DRP[116] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 10 | PLL[1]: DRP[116] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 8 | PLL[1]: DRP[116] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 6 | PLL[1]: DRP[116] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 4 | PLL[1]: DRP[116] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 2 | PLL[1]: DRP[116] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[116] bit 0 | PLL[1]: DRP[116] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 14 | PLL[1]: DRP[115] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 12 | PLL[1]: DRP[115] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 10 | PLL[1]: DRP[115] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 8 | PLL[1]: DRP[115] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 6 | PLL[1]: DRP[115] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 4 | PLL[1]: DRP[115] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 2 | PLL[1]: DRP[115] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[115] bit 0 | PLL[1]: DRP[115] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[114] bit 14 | PLL[1]: DRP[114] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[114] bit 12 | PLL[1]: DRP[114] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[114] bit 10 | PLL[1]: DRP[114] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[114] bit 8 | PLL[1]: DRP[114] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[114] bit 6 | PLL[1]: DRP[114] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: invert CLKINSEL PLL[1]: DRP[114] bit 4 | PLL[1]: DRP[114] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: invert PSINCDEC PLL[1]: DRP[114] bit 2 | PLL[1]: invert PSEN PLL[1]: DRP[114] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: invert RST PLL[1]: DRP[114] bit 0 | PLL[1]: invert PWRDWN PLL[1]: DRP[114] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 14 | PLL[1]: DRP[113] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 12 | PLL[1]: DRP[113] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 10 | PLL[1]: DRP[113] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 8 | PLL[1]: DRP[113] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 6 | PLL[1]: DRP[113] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 4 | PLL[1]: DRP[113] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 2 | PLL[1]: DRP[113] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[113] bit 0 | PLL[1]: DRP[113] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 14 | PLL[1]: DRP[112] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 12 | PLL[1]: DRP[112] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 10 | PLL[1]: DRP[112] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 8 | PLL[1]: DRP[112] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 6 | PLL[1]: DRP[112] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 4 | PLL[1]: DRP[112] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 2 | PLL[1]: DRP[112] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[112] bit 0 | PLL[1]: DRP[112] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 14 | PLL[1]: DRP[127] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 12 | PLL[1]: DRP[127] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 10 | PLL[1]: DRP[127] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 8 | PLL[1]: DRP[127] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 6 | PLL[1]: DRP[127] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 4 | PLL[1]: DRP[127] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 2 | PLL[1]: DRP[127] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[127] bit 0 | PLL[1]: DRP[127] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 14 | PLL[1]: DRP[126] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 12 | PLL[1]: DRP[126] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 10 | PLL[1]: DRP[126] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 8 | PLL[1]: DRP[126] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 6 | PLL[1]: DRP[126] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 4 | PLL[1]: DRP[126] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 2 | PLL[1]: DRP[126] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[126] bit 0 | PLL[1]: DRP[126] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 14 | PLL[1]: DRP[125] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 12 | PLL[1]: DRP[125] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 10 | PLL[1]: DRP[125] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 8 | PLL[1]: DRP[125] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 6 | PLL[1]: DRP[125] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 4 | PLL[1]: DRP[125] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 2 | PLL[1]: DRP[125] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[125] bit 0 | PLL[1]: DRP[125] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 14 | PLL[1]: DRP[124] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 12 | PLL[1]: DRP[124] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 10 | PLL[1]: DRP[124] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 8 | PLL[1]: DRP[124] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 6 | PLL[1]: DRP[124] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 4 | PLL[1]: DRP[124] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 2 | PLL[1]: DRP[124] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[124] bit 0 | PLL[1]: DRP[124] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 14 | PLL[1]: DRP[123] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 12 | PLL[1]: DRP[123] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 10 | PLL[1]: DRP[123] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 8 | PLL[1]: DRP[123] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 6 | PLL[1]: DRP[123] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 4 | PLL[1]: DRP[123] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 2 | PLL[1]: DRP[123] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[123] bit 0 | PLL[1]: DRP[123] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 14 | PLL[1]: DRP[122] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 12 | PLL[1]: DRP[122] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 10 | PLL[1]: DRP[122] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 8 | PLL[1]: DRP[122] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 6 | PLL[1]: DRP[122] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 4 | PLL[1]: DRP[122] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 2 | PLL[1]: DRP[122] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[122] bit 0 | PLL[1]: DRP[122] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 14 | PLL[1]: DRP[121] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 12 | PLL[1]: DRP[121] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 10 | PLL[1]: DRP[121] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 8 | PLL[1]: DRP[121] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 6 | PLL[1]: DRP[121] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 4 | PLL[1]: DRP[121] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 2 | PLL[1]: DRP[121] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[121] bit 0 | PLL[1]: DRP[121] bit 1 | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 14 | PLL[1]: DRP[120] bit 15 | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 12 | PLL[1]: DRP[120] bit 13 | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 10 | PLL[1]: DRP[120] bit 11 | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 8 | PLL[1]: DRP[120] bit 9 | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 6 | PLL[1]: DRP[120] bit 7 | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 4 | PLL[1]: DRP[120] bit 5 | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 2 | PLL[1]: DRP[120] bit 3 | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]: DRP[120] bit 0 | PLL[1]: DRP[120] bit 1 | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | F30 | F31 | F32 | F33 | F34 | F35 | F36 | F37 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[0] | PLL[0]:CONTROL_2[1] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[2] | PLL[0]:CONTROL_2[3] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[4] | PLL[0]:CONTROL_2[5] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[6] | PLL[0]:CONTROL_2[7] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[8] | PLL[0]:CONTROL_2[9] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[10] | PLL[0]:CONTROL_2[11] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[12] | PLL[0]:CONTROL_2[13] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_2[14] | PLL[0]:CONTROL_2[15] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[0] | PLL[0]:CONTROL_3[1] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[2] | PLL[0]:CONTROL_3[3] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[4] | PLL[0]:CONTROL_3[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[6] | PLL[0]:CONTROL_3[7] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[8] | PLL[0]:CONTROL_3[9] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[10] | PLL[0]:CONTROL_3[11] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[12] | PLL[0]:CONTROL_3[13] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_3[14] | PLL[0]:CONTROL_3[15] |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[0] | PLL[0]:CONTROL_4[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[2] | PLL[0]:CONTROL_4[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[4] | PLL[0]:CONTROL_4[5] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[6] | PLL[0]:CONTROL_4[7] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[8] | PLL[0]:CONTROL_4[9] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[10] | PLL[0]:CONTROL_4[11] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[12] | PLL[0]:CONTROL_4[13] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_4[14] | PLL[0]:CONTROL_4[15] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[0] | PLL[0]:CONTROL_5[1] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[2] | PLL[0]:CONTROL_5[3] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[4] | PLL[0]:CONTROL_5[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[6] | PLL[0]:CONTROL_5[7] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[8] | PLL[0]:CONTROL_5[9] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[10] | PLL[0]:CONTROL_5[11] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[12] | PLL[0]:CONTROL_5[13] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_5[14] | PLL[0]:CONTROL_5[15] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:MMCM_EN | PLL[0]:CLOCK_HOLD |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:STARTUP_WAIT | PLL[0]:GTS_WAIT |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CASC_LOCK_EN | PLL[0]:FINE_PS_FRAC[0] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:FINE_PS_FRAC[1] | PLL[0]:FINE_PS_FRAC[2] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:FINE_PS_FRAC[3] | PLL[0]:FINE_PS_FRAC[4] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:FINE_PS_FRAC[5] | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[0] | PLL[0]:CONTROL_0[1] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[2] | PLL[0]:CONTROL_0[3] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[4] | PLL[0]:CONTROL_0[5] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[6] | PLL[0]:CONTROL_0[7] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[8] | PLL[0]:CONTROL_0[9] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[10] | PLL[0]:CONTROL_0[11] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[12] | PLL[0]:CONTROL_0[13] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_0[14] | PLL[0]:CONTROL_0[15] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[0] | PLL[0]:CONTROL_1[1] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[2] | PLL[0]:CONTROL_1[3] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[4] | PLL[0]:CONTROL_1[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[6] | PLL[0]:CONTROL_1[7] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[8] | PLL[0]:CONTROL_1[9] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[10] | PLL[0]:CONTROL_1[11] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[12] | PLL[0]:CONTROL_1[13] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CONTROL_1[14] | PLL[0]:CONTROL_1[15] |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:AVDD_VBG_SEL[0] | PLL[0]:AVDD_VBG_SEL[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:AVDD_VBG_SEL[2] | PLL[0]:AVDD_VBG_SEL[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:AVDD_VBG_PD[0] | PLL[0]:AVDD_VBG_PD[1] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:AVDD_VBG_PD[2] | PLL[0]:AVDD_COMP_SET[0] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:AVDD_COMP_SET[1] | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP_RES[0] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP_RES[1] | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP_BIAS_TRIP_SET |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP[0] | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP[1] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP[2] | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CP[3] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LFHF[0] | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LFHF[1] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:RES[0] | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:RES[1] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:RES[2] | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:RES[3] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:MAN_LF[0] | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:MAN_LF[1] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:MAN_LF[2] | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:VLF_HIGH_DIS_B |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LF_PEN[0] | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LF_PEN[1] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LF_NEN[0] | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LF_NEN[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:VLF_HIGH_PWDN_B | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[0] | - |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[1] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[2] | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[3] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[4] | - |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[6] | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:INTERP_EN[7] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:EN_VCO_DIV6 | PLL[0]:EN_VCO_DIV1 |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:ANALOG_MISC[0] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:ANALOG_MISC[1] | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:ANALOG_MISC[2] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:ANALOG_MISC[3] | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_CNT[0] | PLL[0]:LOCK_CNT[1] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_CNT[2] | PLL[0]:LOCK_CNT[3] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_CNT[4] | PLL[0]:LOCK_CNT[5] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_CNT[6] | PLL[0]:LOCK_CNT[7] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_CNT[8] | PLL[0]:LOCK_CNT[9] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:UNLOCK_CNT[0] | PLL[0]:UNLOCK_CNT[1] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:UNLOCK_CNT[2] | PLL[0]:UNLOCK_CNT[3] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:UNLOCK_CNT[4] | PLL[0]:UNLOCK_CNT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:UNLOCK_CNT[6] | PLL[0]:UNLOCK_CNT[7] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:UNLOCK_CNT[8] | PLL[0]:UNLOCK_CNT[9] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_FB_DLY[0] | PLL[0]:LOCK_FB_DLY[1] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_FB_DLY[2] | PLL[0]:LOCK_FB_DLY[3] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_FB_DLY[4] | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_SAT_HIGH[0] | PLL[0]:LOCK_SAT_HIGH[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_SAT_HIGH[2] | PLL[0]:LOCK_SAT_HIGH[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_SAT_HIGH[4] | PLL[0]:LOCK_SAT_HIGH[5] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_SAT_HIGH[6] | PLL[0]:LOCK_SAT_HIGH[7] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_SAT_HIGH[8] | PLL[0]:LOCK_SAT_HIGH[9] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_REF_DLY[0] | PLL[0]:LOCK_REF_DLY[1] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_REF_DLY[2] | PLL[0]:LOCK_REF_DLY[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:LOCK_REF_DLY[4] | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HVLF_CNT_TEST[0] | PLL[0]:HVLF_CNT_TEST[1] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HVLF_CNT_TEST[2] | PLL[0]:HVLF_CNT_TEST[3] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HVLF_CNT_TEST[4] | PLL[0]:HVLF_CNT_TEST[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HVLF_STEP | PLL[0]:HVLF_CNT_TEST_EN |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:PFD[0] | PLL[0]:PFD[1] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:PFD[2] | PLL[0]:PFD[3] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:PFD[4] | PLL[0]:PFD[5] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:PFD[6] | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DVDD_VBG_SEL[0] | PLL[0]:DVDD_VBG_SEL[1] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DVDD_VBG_SEL[2] | PLL[0]:DVDD_VBG_SEL[3] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DVDD_VBG_PD[0] | PLL[0]:DVDD_VBG_PD[1] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DVDD_VBG_PD[2] | PLL[0]:DVDD_COMP_SET[0] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DVDD_COMP_SET[1] | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_LT[0] | PLL[0]:CLKOUT4_LT[1] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_LT[2] | PLL[0]:CLKOUT4_LT[3] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_LT[4] | PLL[0]:CLKOUT4_LT[5] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_HT[0] | PLL[0]:CLKOUT4_HT[1] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_HT[2] | PLL[0]:CLKOUT4_HT[3] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_HT[4] | PLL[0]:CLKOUT4_HT[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_EN | PLL[0]:CLKOUT4_PM[0] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_PM[1] | PLL[0]:CLKOUT4_PM[2] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_DT[0] | PLL[0]:CLKOUT4_DT[1] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_DT[2] | PLL[0]:CLKOUT4_DT[3] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_DT[4] | PLL[0]:CLKOUT4_DT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_NOCOUNT | PLL[0]:CLKOUT4_EDGE |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT4_MX[0] PLL[0]:CLKOUT4_USE_FINE_PS | PLL[0]:CLKOUT4_CASCADE PLL[0]:CLKOUT4_MX[1] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_LT[0] | PLL[0]:CLKOUT6_LT[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_LT[2] | PLL[0]:CLKOUT6_LT[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_LT[4] | PLL[0]:CLKOUT6_LT[5] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_HT[0] | PLL[0]:CLKOUT6_HT[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_HT[2] | PLL[0]:CLKOUT6_HT[3] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_HT[4] | PLL[0]:CLKOUT6_HT[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_EN | PLL[0]:CLKOUT6_PM[0] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_PM[1] | PLL[0]:CLKOUT6_PM[2] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_DT[0] | PLL[0]:CLKOUT6_DT[1] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_DT[2] | PLL[0]:CLKOUT6_DT[3] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_DT[4] | PLL[0]:CLKOUT6_DT[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_NOCOUNT | PLL[0]:CLKOUT6_EDGE |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_MX[0] PLL[0]:CLKOUT6_USE_FINE_PS | PLL[0]:CLKOUT6_MX[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT6_FRAC_WF | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_LT[0] | PLL[0]:CLKFBOUT_LT[1] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_LT[2] | PLL[0]:CLKFBOUT_LT[3] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_LT[4] | PLL[0]:CLKFBOUT_LT[5] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_HT[0] | PLL[0]:CLKFBOUT_HT[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_HT[2] | PLL[0]:CLKFBOUT_HT[3] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_HT[4] | PLL[0]:CLKFBOUT_HT[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_EN | PLL[0]:CLKFBOUT_PM[0] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_PM[1] | PLL[0]:CLKFBOUT_PM[2] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_DT[0] | PLL[0]:CLKFBOUT_DT[1] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_DT[2] | PLL[0]:CLKFBOUT_DT[3] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_DT[4] | PLL[0]:CLKFBOUT_DT[5] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_NOCOUNT | PLL[0]:CLKFBOUT_EDGE |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_MX[0] PLL[0]:CLKFBOUT_USE_FINE_PS | PLL[0]:CLKFBOUT_MX[1] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_FRAC_WF | PLL[0]:CLKFBOUT_FRAC_EN |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_FRAC[0] | PLL[0]:CLKFBOUT_FRAC[1] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBOUT_FRAC[2] | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_LT[0] | PLL[0]:DIVCLK_LT[1] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_LT[2] | PLL[0]:DIVCLK_LT[3] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_LT[4] | PLL[0]:DIVCLK_LT[5] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_HT[0] | PLL[0]:DIVCLK_HT[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_HT[2] | PLL[0]:DIVCLK_HT[3] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_HT[4] | PLL[0]:DIVCLK_HT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIVCLK_NOCOUNT | PLL[0]:DIVCLK_EDGE |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_LT[0] | PLL[0]:CLKFBIN_LT[1] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_LT[2] | PLL[0]:CLKFBIN_LT[3] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_LT[4] | PLL[0]:CLKFBIN_LT[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_HT[0] | PLL[0]:CLKFBIN_HT[1] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_HT[2] | PLL[0]:CLKFBIN_HT[3] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_HT[4] | PLL[0]:CLKFBIN_HT[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKFBIN_NOCOUNT | PLL[0]:CLKFBIN_EDGE |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_LT[0] | PLL[0]:CLKOUT0_LT[1] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_LT[2] | PLL[0]:CLKOUT0_LT[3] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_LT[4] | PLL[0]:CLKOUT0_LT[5] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_HT[0] | PLL[0]:CLKOUT0_HT[1] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_HT[2] | PLL[0]:CLKOUT0_HT[3] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_HT[4] | PLL[0]:CLKOUT0_HT[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_EN | PLL[0]:CLKOUT0_PM[0] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_PM[1] | PLL[0]:CLKOUT0_PM[2] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_DT[0] | PLL[0]:CLKOUT0_DT[1] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_DT[2] | PLL[0]:CLKOUT0_DT[3] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_DT[4] | PLL[0]:CLKOUT0_DT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_NOCOUNT | PLL[0]:CLKOUT0_EDGE |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_MX[0] PLL[0]:CLKOUT0_USE_FINE_PS | PLL[0]:CLKOUT0_MX[1] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_FRAC_WF | PLL[0]:CLKOUT0_FRAC_EN |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_FRAC[0] | PLL[0]:CLKOUT0_FRAC[1] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT0_FRAC[2] | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_LT[0] | PLL[0]:CLKOUT1_LT[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_LT[2] | PLL[0]:CLKOUT1_LT[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_LT[4] | PLL[0]:CLKOUT1_LT[5] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_HT[0] | PLL[0]:CLKOUT1_HT[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_HT[2] | PLL[0]:CLKOUT1_HT[3] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_HT[4] | PLL[0]:CLKOUT1_HT[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_EN | PLL[0]:CLKOUT1_PM[0] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_PM[1] | PLL[0]:CLKOUT1_PM[2] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_DT[0] | PLL[0]:CLKOUT1_DT[1] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_DT[2] | PLL[0]:CLKOUT1_DT[3] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_DT[4] | PLL[0]:CLKOUT1_DT[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_NOCOUNT | PLL[0]:CLKOUT1_EDGE |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT1_MX[0] PLL[0]:CLKOUT1_USE_FINE_PS | PLL[0]:CLKOUT1_MX[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_LT[0] | PLL[0]:CLKOUT2_LT[1] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_LT[2] | PLL[0]:CLKOUT2_LT[3] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_LT[4] | PLL[0]:CLKOUT2_LT[5] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_HT[0] | PLL[0]:CLKOUT2_HT[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_HT[2] | PLL[0]:CLKOUT2_HT[3] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_HT[4] | PLL[0]:CLKOUT2_HT[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_EN | PLL[0]:CLKOUT2_PM[0] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_PM[1] | PLL[0]:CLKOUT2_PM[2] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_DT[0] | PLL[0]:CLKOUT2_DT[1] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_DT[2] | PLL[0]:CLKOUT2_DT[3] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_DT[4] | PLL[0]:CLKOUT2_DT[5] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_NOCOUNT | PLL[0]:CLKOUT2_EDGE |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT2_MX[0] PLL[0]:CLKOUT2_USE_FINE_PS | PLL[0]:CLKOUT2_MX[1] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_LT[0] | PLL[0]:CLKOUT3_LT[1] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_LT[2] | PLL[0]:CLKOUT3_LT[3] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_LT[4] | PLL[0]:CLKOUT3_LT[5] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_HT[0] | PLL[0]:CLKOUT3_HT[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_HT[2] | PLL[0]:CLKOUT3_HT[3] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_HT[4] | PLL[0]:CLKOUT3_HT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_EN | PLL[0]:CLKOUT3_PM[0] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_PM[1] | PLL[0]:CLKOUT3_PM[2] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_DT[0] | PLL[0]:CLKOUT3_DT[1] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_DT[2] | PLL[0]:CLKOUT3_DT[3] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_DT[4] | PLL[0]:CLKOUT3_DT[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_NOCOUNT | PLL[0]:CLKOUT3_EDGE |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT3_MX[0] PLL[0]:CLKOUT3_USE_FINE_PS | PLL[0]:CLKOUT3_MX[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_CVDD[0] | PLL[0]:IN_DLY_MX_CVDD[1] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_CVDD[2] | PLL[0]:IN_DLY_MX_CVDD[3] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_CVDD[4] | PLL[0]:IN_DLY_MX_CVDD[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HROW_DLY_SET[0] | PLL[0]:HROW_DLY_SET[1] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:HROW_DLY_SET[2] | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:SYNTH_CLK_DIV[0] | PLL[0]:SYNTH_CLK_DIV[1] |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKBURST_CNT[0] | PLL[0]:CLKBURST_CNT[1] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKBURST_CNT[2] | PLL[0]:CLKBURST_CNT[3] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKBURST_ENABLE | PLL[0]:CLKBURST_REPEAT |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:TMUX_MUX_SEL[0] | PLL[0]:TMUX_MUX_SEL[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:DIRECT_PATH_CNTRL |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_DVDD[0] | PLL[0]:IN_DLY_MX_DVDD[1] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_DVDD[2] | PLL[0]:IN_DLY_MX_DVDD[3] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_MX_DVDD[4] | PLL[0]:IN_DLY_MX_DVDD[5] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_SET[0] | PLL[0]:IN_DLY_SET[1] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_SET[2] | PLL[0]:IN_DLY_SET[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:IN_DLY_SET[4] | PLL[0]:IN_DLY_EN |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_LT[0] | PLL[0]:CLKOUT5_LT[1] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_LT[2] | PLL[0]:CLKOUT5_LT[3] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_LT[4] | PLL[0]:CLKOUT5_LT[5] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_HT[0] | PLL[0]:CLKOUT5_HT[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_HT[2] | PLL[0]:CLKOUT5_HT[3] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_HT[4] | PLL[0]:CLKOUT5_HT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_EN | PLL[0]:CLKOUT5_PM[0] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_PM[1] | PLL[0]:CLKOUT5_PM[2] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_DT[0] | PLL[0]:CLKOUT5_DT[1] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_DT[2] | PLL[0]:CLKOUT5_DT[3] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_DT[4] | PLL[0]:CLKOUT5_DT[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_NOCOUNT | PLL[0]:CLKOUT5_EDGE |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_MX[0] PLL[0]:CLKOUT5_USE_FINE_PS | PLL[0]:CLKOUT5_MX[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[0]:CLKOUT5_FRAC_WF | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_FRAC_WF | - |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_MX[0] PLL[1]:CLKOUT5_USE_FINE_PS | PLL[1]:CLKOUT5_MX[1] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_NOCOUNT | PLL[1]:CLKOUT5_EDGE |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_DT[4] | PLL[1]:CLKOUT5_DT[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_DT[2] | PLL[1]:CLKOUT5_DT[3] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_DT[0] | PLL[1]:CLKOUT5_DT[1] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_PM[1] | PLL[1]:CLKOUT5_PM[2] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_EN | PLL[1]:CLKOUT5_PM[0] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_HT[4] | PLL[1]:CLKOUT5_HT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_HT[2] | PLL[1]:CLKOUT5_HT[3] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_HT[0] | PLL[1]:CLKOUT5_HT[1] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_LT[4] | PLL[1]:CLKOUT5_LT[5] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_LT[2] | PLL[1]:CLKOUT5_LT[3] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT5_LT[0] | PLL[1]:CLKOUT5_LT[1] |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_SET[4] | PLL[1]:IN_DLY_EN |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_SET[2] | PLL[1]:IN_DLY_SET[3] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_SET[0] | PLL[1]:IN_DLY_SET[1] |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_DVDD[4] | PLL[1]:IN_DLY_MX_DVDD[5] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_DVDD[2] | PLL[1]:IN_DLY_MX_DVDD[3] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_DVDD[0] | PLL[1]:IN_DLY_MX_DVDD[1] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIRECT_PATH_CNTRL |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:TMUX_MUX_SEL[0] | PLL[1]:TMUX_MUX_SEL[1] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKBURST_ENABLE | PLL[1]:CLKBURST_REPEAT |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKBURST_CNT[2] | PLL[1]:CLKBURST_CNT[3] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKBURST_CNT[0] | PLL[1]:CLKBURST_CNT[1] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:SYNTH_CLK_DIV[0] | PLL[1]:SYNTH_CLK_DIV[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HROW_DLY_SET[2] | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HROW_DLY_SET[0] | PLL[1]:HROW_DLY_SET[1] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_CVDD[4] | PLL[1]:IN_DLY_MX_CVDD[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_CVDD[2] | PLL[1]:IN_DLY_MX_CVDD[3] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:IN_DLY_MX_CVDD[0] | PLL[1]:IN_DLY_MX_CVDD[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_MX[0] PLL[1]:CLKOUT3_USE_FINE_PS | PLL[1]:CLKOUT3_MX[1] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_NOCOUNT | PLL[1]:CLKOUT3_EDGE |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_DT[4] | PLL[1]:CLKOUT3_DT[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_DT[2] | PLL[1]:CLKOUT3_DT[3] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_DT[0] | PLL[1]:CLKOUT3_DT[1] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_PM[1] | PLL[1]:CLKOUT3_PM[2] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_EN | PLL[1]:CLKOUT3_PM[0] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_HT[4] | PLL[1]:CLKOUT3_HT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_HT[2] | PLL[1]:CLKOUT3_HT[3] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_HT[0] | PLL[1]:CLKOUT3_HT[1] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_LT[4] | PLL[1]:CLKOUT3_LT[5] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_LT[2] | PLL[1]:CLKOUT3_LT[3] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT3_LT[0] | PLL[1]:CLKOUT3_LT[1] |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_MX[0] PLL[1]:CLKOUT2_USE_FINE_PS | PLL[1]:CLKOUT2_MX[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_NOCOUNT | PLL[1]:CLKOUT2_EDGE |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_DT[4] | PLL[1]:CLKOUT2_DT[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_DT[2] | PLL[1]:CLKOUT2_DT[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_DT[0] | PLL[1]:CLKOUT2_DT[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_PM[1] | PLL[1]:CLKOUT2_PM[2] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_EN | PLL[1]:CLKOUT2_PM[0] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_HT[4] | PLL[1]:CLKOUT2_HT[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_HT[2] | PLL[1]:CLKOUT2_HT[3] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_HT[0] | PLL[1]:CLKOUT2_HT[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_LT[4] | PLL[1]:CLKOUT2_LT[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_LT[2] | PLL[1]:CLKOUT2_LT[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT2_LT[0] | PLL[1]:CLKOUT2_LT[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_MX[0] PLL[1]:CLKOUT1_USE_FINE_PS | PLL[1]:CLKOUT1_MX[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_NOCOUNT | PLL[1]:CLKOUT1_EDGE |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_DT[4] | PLL[1]:CLKOUT1_DT[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_DT[2] | PLL[1]:CLKOUT1_DT[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_DT[0] | PLL[1]:CLKOUT1_DT[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_PM[1] | PLL[1]:CLKOUT1_PM[2] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_EN | PLL[1]:CLKOUT1_PM[0] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_HT[4] | PLL[1]:CLKOUT1_HT[5] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_HT[2] | PLL[1]:CLKOUT1_HT[3] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_HT[0] | PLL[1]:CLKOUT1_HT[1] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_LT[4] | PLL[1]:CLKOUT1_LT[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_LT[2] | PLL[1]:CLKOUT1_LT[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT1_LT[0] | PLL[1]:CLKOUT1_LT[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_FRAC[2] | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_FRAC[0] | PLL[1]:CLKOUT0_FRAC[1] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_FRAC_WF | PLL[1]:CLKOUT0_FRAC_EN |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_MX[0] PLL[1]:CLKOUT0_USE_FINE_PS | PLL[1]:CLKOUT0_MX[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_NOCOUNT | PLL[1]:CLKOUT0_EDGE |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_DT[4] | PLL[1]:CLKOUT0_DT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_DT[2] | PLL[1]:CLKOUT0_DT[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_DT[0] | PLL[1]:CLKOUT0_DT[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_PM[1] | PLL[1]:CLKOUT0_PM[2] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_EN | PLL[1]:CLKOUT0_PM[0] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_HT[4] | PLL[1]:CLKOUT0_HT[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_HT[2] | PLL[1]:CLKOUT0_HT[3] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_HT[0] | PLL[1]:CLKOUT0_HT[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_LT[4] | PLL[1]:CLKOUT0_LT[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_LT[2] | PLL[1]:CLKOUT0_LT[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT0_LT[0] | PLL[1]:CLKOUT0_LT[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_NOCOUNT | PLL[1]:CLKFBIN_EDGE |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_HT[4] | PLL[1]:CLKFBIN_HT[5] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_HT[2] | PLL[1]:CLKFBIN_HT[3] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_HT[0] | PLL[1]:CLKFBIN_HT[1] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_LT[4] | PLL[1]:CLKFBIN_LT[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_LT[2] | PLL[1]:CLKFBIN_LT[3] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBIN_LT[0] | PLL[1]:CLKFBIN_LT[1] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_NOCOUNT | PLL[1]:DIVCLK_EDGE |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_HT[4] | PLL[1]:DIVCLK_HT[5] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_HT[2] | PLL[1]:DIVCLK_HT[3] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_HT[0] | PLL[1]:DIVCLK_HT[1] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_LT[4] | PLL[1]:DIVCLK_LT[5] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_LT[2] | PLL[1]:DIVCLK_LT[3] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DIVCLK_LT[0] | PLL[1]:DIVCLK_LT[1] |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_FRAC[2] | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_FRAC[0] | PLL[1]:CLKFBOUT_FRAC[1] |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_FRAC_WF | PLL[1]:CLKFBOUT_FRAC_EN |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_MX[0] PLL[1]:CLKFBOUT_USE_FINE_PS | PLL[1]:CLKFBOUT_MX[1] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_NOCOUNT | PLL[1]:CLKFBOUT_EDGE |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_DT[4] | PLL[1]:CLKFBOUT_DT[5] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_DT[2] | PLL[1]:CLKFBOUT_DT[3] |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_DT[0] | PLL[1]:CLKFBOUT_DT[1] |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_PM[1] | PLL[1]:CLKFBOUT_PM[2] |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_EN | PLL[1]:CLKFBOUT_PM[0] |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_HT[4] | PLL[1]:CLKFBOUT_HT[5] |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_HT[2] | PLL[1]:CLKFBOUT_HT[3] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_HT[0] | PLL[1]:CLKFBOUT_HT[1] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_LT[4] | PLL[1]:CLKFBOUT_LT[5] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_LT[2] | PLL[1]:CLKFBOUT_LT[3] |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKFBOUT_LT[0] | PLL[1]:CLKFBOUT_LT[1] |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_FRAC_WF | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_MX[0] PLL[1]:CLKOUT6_USE_FINE_PS | PLL[1]:CLKOUT6_MX[1] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_NOCOUNT | PLL[1]:CLKOUT6_EDGE |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_DT[4] | PLL[1]:CLKOUT6_DT[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_DT[2] | PLL[1]:CLKOUT6_DT[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_DT[0] | PLL[1]:CLKOUT6_DT[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_PM[1] | PLL[1]:CLKOUT6_PM[2] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_EN | PLL[1]:CLKOUT6_PM[0] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_HT[4] | PLL[1]:CLKOUT6_HT[5] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_HT[2] | PLL[1]:CLKOUT6_HT[3] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_HT[0] | PLL[1]:CLKOUT6_HT[1] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_LT[4] | PLL[1]:CLKOUT6_LT[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_LT[2] | PLL[1]:CLKOUT6_LT[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT6_LT[0] | PLL[1]:CLKOUT6_LT[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_MX[0] PLL[1]:CLKOUT4_USE_FINE_PS | PLL[1]:CLKOUT4_CASCADE PLL[1]:CLKOUT4_MX[1] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_NOCOUNT | PLL[1]:CLKOUT4_EDGE |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_DT[4] | PLL[1]:CLKOUT4_DT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_DT[2] | PLL[1]:CLKOUT4_DT[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_DT[0] | PLL[1]:CLKOUT4_DT[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_PM[1] | PLL[1]:CLKOUT4_PM[2] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_EN | PLL[1]:CLKOUT4_PM[0] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_HT[4] | PLL[1]:CLKOUT4_HT[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_HT[2] | PLL[1]:CLKOUT4_HT[3] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_HT[0] | PLL[1]:CLKOUT4_HT[1] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_LT[4] | PLL[1]:CLKOUT4_LT[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_LT[2] | PLL[1]:CLKOUT4_LT[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CLKOUT4_LT[0] | PLL[1]:CLKOUT4_LT[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DVDD_COMP_SET[1] | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DVDD_VBG_PD[2] | PLL[1]:DVDD_COMP_SET[0] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DVDD_VBG_PD[0] | PLL[1]:DVDD_VBG_PD[1] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DVDD_VBG_SEL[2] | PLL[1]:DVDD_VBG_SEL[3] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:DVDD_VBG_SEL[0] | PLL[1]:DVDD_VBG_SEL[1] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:PFD[6] | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:PFD[4] | PLL[1]:PFD[5] |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:PFD[2] | PLL[1]:PFD[3] |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:PFD[0] | PLL[1]:PFD[1] |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HVLF_STEP | PLL[1]:HVLF_CNT_TEST_EN |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HVLF_CNT_TEST[4] | PLL[1]:HVLF_CNT_TEST[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HVLF_CNT_TEST[2] | PLL[1]:HVLF_CNT_TEST[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:HVLF_CNT_TEST[0] | PLL[1]:HVLF_CNT_TEST[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_REF_DLY[4] | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_REF_DLY[2] | PLL[1]:LOCK_REF_DLY[3] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_REF_DLY[0] | PLL[1]:LOCK_REF_DLY[1] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_SAT_HIGH[8] | PLL[1]:LOCK_SAT_HIGH[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_SAT_HIGH[6] | PLL[1]:LOCK_SAT_HIGH[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_SAT_HIGH[4] | PLL[1]:LOCK_SAT_HIGH[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_SAT_HIGH[2] | PLL[1]:LOCK_SAT_HIGH[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_SAT_HIGH[0] | PLL[1]:LOCK_SAT_HIGH[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_FB_DLY[4] | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_FB_DLY[2] | PLL[1]:LOCK_FB_DLY[3] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_FB_DLY[0] | PLL[1]:LOCK_FB_DLY[1] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:UNLOCK_CNT[8] | PLL[1]:UNLOCK_CNT[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:UNLOCK_CNT[6] | PLL[1]:UNLOCK_CNT[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:UNLOCK_CNT[4] | PLL[1]:UNLOCK_CNT[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:UNLOCK_CNT[2] | PLL[1]:UNLOCK_CNT[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:UNLOCK_CNT[0] | PLL[1]:UNLOCK_CNT[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_CNT[8] | PLL[1]:LOCK_CNT[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_CNT[6] | PLL[1]:LOCK_CNT[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_CNT[4] | PLL[1]:LOCK_CNT[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_CNT[2] | PLL[1]:LOCK_CNT[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LOCK_CNT[0] | PLL[1]:LOCK_CNT[1] |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:ANALOG_MISC[3] | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:ANALOG_MISC[2] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:ANALOG_MISC[1] | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:ANALOG_MISC[0] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:EN_VCO_DIV6 | PLL[1]:EN_VCO_DIV1 |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[7] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[6] | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[5] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[4] | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[3] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[2] | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[1] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:INTERP_EN[0] | - |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:VLF_HIGH_PWDN_B | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LF_NEN[1] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LF_NEN[0] | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LF_PEN[1] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LF_PEN[0] | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:VLF_HIGH_DIS_B |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:MAN_LF[2] | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:MAN_LF[1] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:MAN_LF[0] | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:RES[3] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:RES[2] | - |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:RES[1] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:RES[0] | - |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LFHF[1] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:LFHF[0] | - |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP[3] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP[2] | - |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP[1] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP[0] | - |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP_BIAS_TRIP_SET |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP_RES[1] | - |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CP_RES[0] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:AVDD_COMP_SET[1] | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:AVDD_VBG_PD[2] | PLL[1]:AVDD_COMP_SET[0] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:AVDD_VBG_PD[0] | PLL[1]:AVDD_VBG_PD[1] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:AVDD_VBG_SEL[2] | PLL[1]:AVDD_VBG_SEL[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:AVDD_VBG_SEL[0] | PLL[1]:AVDD_VBG_SEL[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame |
|---|
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B63 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[14] | PLL[1]:CONTROL_1[15] |
| B62 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[12] | PLL[1]:CONTROL_1[13] |
| B61 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[10] | PLL[1]:CONTROL_1[11] |
| B60 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[8] | PLL[1]:CONTROL_1[9] |
| B59 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[6] | PLL[1]:CONTROL_1[7] |
| B58 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[4] | PLL[1]:CONTROL_1[5] |
| B57 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[2] | PLL[1]:CONTROL_1[3] |
| B56 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_1[0] | PLL[1]:CONTROL_1[1] |
| B55 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[14] | PLL[1]:CONTROL_0[15] |
| B54 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[12] | PLL[1]:CONTROL_0[13] |
| B53 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[10] | PLL[1]:CONTROL_0[11] |
| B52 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[8] | PLL[1]:CONTROL_0[9] |
| B51 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[6] | PLL[1]:CONTROL_0[7] |
| B50 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[4] | PLL[1]:CONTROL_0[5] |
| B49 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[2] | PLL[1]:CONTROL_0[3] |
| B48 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_0[0] | PLL[1]:CONTROL_0[1] |
| B47 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B46 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B45 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B44 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B43 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B42 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B41 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B40 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B39 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B38 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B37 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:FINE_PS_FRAC[5] | - |
| B36 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:FINE_PS_FRAC[3] | PLL[1]:FINE_PS_FRAC[4] |
| B35 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:FINE_PS_FRAC[1] | PLL[1]:FINE_PS_FRAC[2] |
| B34 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CASC_LOCK_EN | PLL[1]:FINE_PS_FRAC[0] |
| B33 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:STARTUP_WAIT | PLL[1]:GTS_WAIT |
| B32 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:MMCM_EN | PLL[1]:CLOCK_HOLD |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| Bit | Frame | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[14] | PLL[1]:CONTROL_5[15] |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[12] | PLL[1]:CONTROL_5[13] |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[10] | PLL[1]:CONTROL_5[11] |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[8] | PLL[1]:CONTROL_5[9] |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[6] | PLL[1]:CONTROL_5[7] |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[4] | PLL[1]:CONTROL_5[5] |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[2] | PLL[1]:CONTROL_5[3] |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_5[0] | PLL[1]:CONTROL_5[1] |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[14] | PLL[1]:CONTROL_4[15] |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[12] | PLL[1]:CONTROL_4[13] |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[10] | PLL[1]:CONTROL_4[11] |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[8] | PLL[1]:CONTROL_4[9] |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[6] | PLL[1]:CONTROL_4[7] |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[4] | PLL[1]:CONTROL_4[5] |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[2] | PLL[1]:CONTROL_4[3] |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_4[0] | PLL[1]:CONTROL_4[1] |
| B15 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[14] | PLL[1]:CONTROL_3[15] |
| B14 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[12] | PLL[1]:CONTROL_3[13] |
| B13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[10] | PLL[1]:CONTROL_3[11] |
| B12 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[8] | PLL[1]:CONTROL_3[9] |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[6] | PLL[1]:CONTROL_3[7] |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[4] | PLL[1]:CONTROL_3[5] |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[2] | PLL[1]:CONTROL_3[3] |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_3[0] | PLL[1]:CONTROL_3[1] |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[14] | PLL[1]:CONTROL_2[15] |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[12] | PLL[1]:CONTROL_2[13] |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[10] | PLL[1]:CONTROL_2[11] |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[8] | PLL[1]:CONTROL_2[9] |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[6] | PLL[1]:CONTROL_2[7] |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[4] | PLL[1]:CONTROL_2[5] |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[2] | PLL[1]:CONTROL_2[3] |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | PLL[1]:CONTROL_2[0] | PLL[1]:CONTROL_2[1] |
| PLL[0]:ANALOG_MISC | 13.F26.B11 | 13.F27.B12 | 13.F26.B13 | 13.F27.B14 |
|---|---|---|---|---|
| PLL[0]:AVDD_VBG_SEL | 8.F27.B46 | 8.F26.B46 | 8.F27.B47 | 8.F26.B47 |
| PLL[0]:CLKBURST_CNT | 17.F27.B26 | 17.F26.B26 | 17.F27.B27 | 17.F26.B27 |
| PLL[0]:CP | 8.F27.B8 | 8.F26.B9 | 8.F27.B10 | 8.F26.B11 |
| PLL[0]:DVDD_VBG_SEL | 14.F27.B6 | 14.F26.B6 | 14.F27.B7 | 14.F26.B7 |
| PLL[0]:RES | 8.F27.B0 | 8.F26.B1 | 8.F27.B2 | 8.F26.B3 |
| PLL[1]:ANALOG_MISC | 26.F26.B52 | 26.F27.B51 | 26.F26.B50 | 26.F27.B49 |
| PLL[1]:AVDD_VBG_SEL | 31.F27.B17 | 31.F26.B17 | 31.F27.B16 | 31.F26.B16 |
| PLL[1]:CLKBURST_CNT | 22.F27.B37 | 22.F26.B37 | 22.F27.B36 | 22.F26.B36 |
| PLL[1]:CP | 31.F27.B55 | 31.F26.B54 | 31.F27.B53 | 31.F26.B52 |
| PLL[1]:DVDD_VBG_SEL | 25.F27.B57 | 25.F26.B57 | 25.F27.B56 | 25.F26.B56 |
| PLL[1]:RES | 31.F27.B63 | 31.F26.B62 | 31.F27.B61 | 31.F26.B60 |
| non-inverted | [3] | [2] | [1] | [0] |
| PLL[0]:AVDD_COMP_SET | 8.F26.B43 | 8.F27.B44 |
|---|---|---|
| PLL[0]:CLKFBOUT_MX | 15.F27.B19 | 15.F26.B19 |
| PLL[0]:CLKOUT0_MX | 16.F27.B51 | 16.F26.B51 |
| PLL[0]:CLKOUT1_MX | 16.F27.B35 | 16.F26.B35 |
| PLL[0]:CLKOUT2_MX | 16.F27.B19 | 16.F26.B19 |
| PLL[0]:CLKOUT3_MX | 16.F27.B3 | 16.F26.B3 |
| PLL[0]:CLKOUT4_MX | 15.F27.B51 | 15.F26.B51 |
| PLL[0]:CLKOUT5_MX | 17.F27.B3 | 17.F26.B3 |
| PLL[0]:CLKOUT6_MX | 15.F27.B35 | 15.F26.B35 |
| PLL[0]:CP_RES | 8.F26.B13 | 8.F27.B14 |
| PLL[0]:DVDD_COMP_SET | 14.F26.B3 | 14.F27.B4 |
| PLL[0]:LFHF | 8.F27.B4 | 8.F26.B5 |
| PLL[0]:LF_NEN | 9.F27.B40 | 9.F26.B41 |
| PLL[0]:LF_PEN | 9.F27.B42 | 9.F26.B43 |
| PLL[0]:SYNTH_CLK_DIV | 17.F27.B47 | 17.F26.B47 |
| PLL[0]:TMUX_MUX_SEL | 17.F27.B24 | 17.F26.B24 |
| PLL[1]:AVDD_COMP_SET | 31.F26.B20 | 31.F27.B19 |
| PLL[1]:CLKFBOUT_MX | 24.F27.B44 | 24.F26.B44 |
| PLL[1]:CLKOUT0_MX | 23.F27.B12 | 23.F26.B12 |
| PLL[1]:CLKOUT1_MX | 23.F27.B28 | 23.F26.B28 |
| PLL[1]:CLKOUT2_MX | 23.F27.B44 | 23.F26.B44 |
| PLL[1]:CLKOUT3_MX | 23.F27.B60 | 23.F26.B60 |
| PLL[1]:CLKOUT4_MX | 24.F27.B12 | 24.F26.B12 |
| PLL[1]:CLKOUT5_MX | 22.F27.B60 | 22.F26.B60 |
| PLL[1]:CLKOUT6_MX | 24.F27.B28 | 24.F26.B28 |
| PLL[1]:CP_RES | 31.F26.B50 | 31.F27.B49 |
| PLL[1]:DVDD_COMP_SET | 25.F26.B60 | 25.F27.B59 |
| PLL[1]:LFHF | 31.F27.B59 | 31.F26.B58 |
| PLL[1]:LF_NEN | 30.F27.B23 | 30.F26.B22 |
| PLL[1]:LF_PEN | 30.F27.B21 | 30.F26.B20 |
| PLL[1]:SYNTH_CLK_DIV | 22.F27.B16 | 22.F26.B16 |
| PLL[1]:TMUX_MUX_SEL | 22.F27.B39 | 22.F26.B39 |
| non-inverted | [1] | [0] |
| PLL[0]:AVDD_VBG_PD | 8.F26.B44 | 8.F27.B45 | 8.F26.B45 |
|---|---|---|---|
| PLL[0]:CLKFBOUT_FRAC | 15.F26.B16 | 15.F27.B17 | 15.F26.B17 |
| PLL[0]:CLKFBOUT_PM | 15.F27.B24 | 15.F26.B24 | 15.F27.B25 |
| PLL[0]:CLKOUT0_FRAC | 16.F26.B48 | 16.F27.B49 | 16.F26.B49 |
| PLL[0]:CLKOUT0_PM | 16.F27.B56 | 16.F26.B56 | 16.F27.B57 |
| PLL[0]:CLKOUT1_PM | 16.F27.B40 | 16.F26.B40 | 16.F27.B41 |
| PLL[0]:CLKOUT2_PM | 16.F27.B24 | 16.F26.B24 | 16.F27.B25 |
| PLL[0]:CLKOUT3_PM | 16.F27.B8 | 16.F26.B8 | 16.F27.B9 |
| PLL[0]:CLKOUT4_PM | 15.F27.B56 | 15.F26.B56 | 15.F27.B57 |
| PLL[0]:CLKOUT5_PM | 17.F27.B8 | 17.F26.B8 | 17.F27.B9 |
| PLL[0]:CLKOUT6_PM | 15.F27.B40 | 15.F26.B40 | 15.F27.B41 |
| PLL[0]:DVDD_VBG_PD | 14.F26.B4 | 14.F27.B5 | 14.F26.B5 |
| PLL[0]:HROW_DLY_SET | 17.F26.B56 | 17.F27.B57 | 17.F26.B57 |
| PLL[0]:MAN_LF | 9.F26.B45 | 9.F27.B46 | 9.F26.B47 |
| PLL[1]:AVDD_VBG_PD | 31.F26.B19 | 31.F27.B18 | 31.F26.B18 |
| PLL[1]:CLKFBOUT_FRAC | 24.F26.B47 | 24.F27.B46 | 24.F26.B46 |
| PLL[1]:CLKFBOUT_PM | 24.F27.B39 | 24.F26.B39 | 24.F27.B38 |
| PLL[1]:CLKOUT0_FRAC | 23.F26.B15 | 23.F27.B14 | 23.F26.B14 |
| PLL[1]:CLKOUT0_PM | 23.F27.B7 | 23.F26.B7 | 23.F27.B6 |
| PLL[1]:CLKOUT1_PM | 23.F27.B23 | 23.F26.B23 | 23.F27.B22 |
| PLL[1]:CLKOUT2_PM | 23.F27.B39 | 23.F26.B39 | 23.F27.B38 |
| PLL[1]:CLKOUT3_PM | 23.F27.B55 | 23.F26.B55 | 23.F27.B54 |
| PLL[1]:CLKOUT4_PM | 24.F27.B7 | 24.F26.B7 | 24.F27.B6 |
| PLL[1]:CLKOUT5_PM | 22.F27.B55 | 22.F26.B55 | 22.F27.B54 |
| PLL[1]:CLKOUT6_PM | 24.F27.B23 | 24.F26.B23 | 24.F27.B22 |
| PLL[1]:DVDD_VBG_PD | 25.F26.B59 | 25.F27.B58 | 25.F26.B58 |
| PLL[1]:HROW_DLY_SET | 22.F26.B7 | 22.F27.B6 | 22.F26.B6 |
| PLL[1]:MAN_LF | 30.F26.B18 | 30.F27.B17 | 30.F26.B16 |
| non-inverted | [2] | [1] | [0] |
| PLL[0]:CASC_LOCK_EN | 3.F26.B29 |
|---|---|
| PLL[0]:CLKBURST_ENABLE | 17.F26.B25 |
| PLL[0]:CLKBURST_REPEAT | 17.F27.B25 |
| PLL[0]:CLKFBIN_EDGE | 15.F27.B1 |
| PLL[0]:CLKFBIN_NOCOUNT | 15.F26.B1 |
| PLL[0]:CLKFBOUT_EDGE | 15.F27.B20 |
| PLL[0]:CLKFBOUT_EN | 15.F26.B25 |
| PLL[0]:CLKFBOUT_FRAC_EN | 15.F27.B18 |
| PLL[0]:CLKFBOUT_FRAC_WF | 15.F26.B18 |
| PLL[0]:CLKFBOUT_NOCOUNT | 15.F26.B20 |
| PLL[0]:CLKFBOUT_USE_FINE_PS | 15.F26.B19 |
| PLL[0]:CLKOUT0_EDGE | 16.F27.B52 |
| PLL[0]:CLKOUT0_EN | 16.F26.B57 |
| PLL[0]:CLKOUT0_FRAC_EN | 16.F27.B50 |
| PLL[0]:CLKOUT0_FRAC_WF | 16.F26.B50 |
| PLL[0]:CLKOUT0_NOCOUNT | 16.F26.B52 |
| PLL[0]:CLKOUT0_USE_FINE_PS | 16.F26.B51 |
| PLL[0]:CLKOUT1_EDGE | 16.F27.B36 |
| PLL[0]:CLKOUT1_EN | 16.F26.B41 |
| PLL[0]:CLKOUT1_NOCOUNT | 16.F26.B36 |
| PLL[0]:CLKOUT1_USE_FINE_PS | 16.F26.B35 |
| PLL[0]:CLKOUT2_EDGE | 16.F27.B20 |
| PLL[0]:CLKOUT2_EN | 16.F26.B25 |
| PLL[0]:CLKOUT2_NOCOUNT | 16.F26.B20 |
| PLL[0]:CLKOUT2_USE_FINE_PS | 16.F26.B19 |
| PLL[0]:CLKOUT3_EDGE | 16.F27.B4 |
| PLL[0]:CLKOUT3_EN | 16.F26.B9 |
| PLL[0]:CLKOUT3_NOCOUNT | 16.F26.B4 |
| PLL[0]:CLKOUT3_USE_FINE_PS | 16.F26.B3 |
| PLL[0]:CLKOUT4_CASCADE | 15.F27.B51 |
| PLL[0]:CLKOUT4_EDGE | 15.F27.B52 |
| PLL[0]:CLKOUT4_EN | 15.F26.B57 |
| PLL[0]:CLKOUT4_NOCOUNT | 15.F26.B52 |
| PLL[0]:CLKOUT4_USE_FINE_PS | 15.F26.B51 |
| PLL[0]:CLKOUT5_EDGE | 17.F27.B4 |
| PLL[0]:CLKOUT5_EN | 17.F26.B9 |
| PLL[0]:CLKOUT5_FRAC_WF | 17.F26.B2 |
| PLL[0]:CLKOUT5_NOCOUNT | 17.F26.B4 |
| PLL[0]:CLKOUT5_USE_FINE_PS | 17.F26.B3 |
| PLL[0]:CLKOUT6_EDGE | 15.F27.B36 |
| PLL[0]:CLKOUT6_EN | 15.F26.B41 |
| PLL[0]:CLKOUT6_FRAC_WF | 15.F26.B34 |
| PLL[0]:CLKOUT6_NOCOUNT | 15.F26.B36 |
| PLL[0]:CLKOUT6_USE_FINE_PS | 15.F26.B35 |
| PLL[0]:CLOCK_HOLD | 3.F27.B31 |
| PLL[0]:CP_BIAS_TRIP_SET | 8.F27.B12 |
| PLL[0]:DIRECT_PATH_CNTRL | 17.F27.B22 |
| PLL[0]:DIVCLK_EDGE | 15.F27.B9 |
| PLL[0]:DIVCLK_NOCOUNT | 15.F26.B9 |
| PLL[0]:EN_VCO_DIV1 | 13.F27.B47 |
| PLL[0]:EN_VCO_DIV6 | 13.F26.B47 |
| PLL[0]:GTS_WAIT | 3.F27.B30 |
| PLL[0]:HVLF_CNT_TEST_EN | 14.F27.B36 |
| PLL[0]:HVLF_STEP | 14.F26.B36 |
| PLL[0]:IN_DLY_EN | 17.F27.B16 |
| PLL[0]:MMCM_EN | 3.F26.B31 |
| PLL[0]:STARTUP_WAIT | 3.F26.B30 |
| PLL[0]:VLF_HIGH_DIS_B | 9.F27.B44 |
| PLL[0]:VLF_HIGH_PWDN_B | 9.F26.B15 |
| PLL[1]:CASC_LOCK_EN | 36.F26.B34 |
| PLL[1]:CLKBURST_ENABLE | 22.F26.B38 |
| PLL[1]:CLKBURST_REPEAT | 22.F27.B38 |
| PLL[1]:CLKFBIN_EDGE | 24.F27.B62 |
| PLL[1]:CLKFBIN_NOCOUNT | 24.F26.B62 |
| PLL[1]:CLKFBOUT_EDGE | 24.F27.B43 |
| PLL[1]:CLKFBOUT_EN | 24.F26.B38 |
| PLL[1]:CLKFBOUT_FRAC_EN | 24.F27.B45 |
| PLL[1]:CLKFBOUT_FRAC_WF | 24.F26.B45 |
| PLL[1]:CLKFBOUT_NOCOUNT | 24.F26.B43 |
| PLL[1]:CLKFBOUT_USE_FINE_PS | 24.F26.B44 |
| PLL[1]:CLKOUT0_EDGE | 23.F27.B11 |
| PLL[1]:CLKOUT0_EN | 23.F26.B6 |
| PLL[1]:CLKOUT0_FRAC_EN | 23.F27.B13 |
| PLL[1]:CLKOUT0_FRAC_WF | 23.F26.B13 |
| PLL[1]:CLKOUT0_NOCOUNT | 23.F26.B11 |
| PLL[1]:CLKOUT0_USE_FINE_PS | 23.F26.B12 |
| PLL[1]:CLKOUT1_EDGE | 23.F27.B27 |
| PLL[1]:CLKOUT1_EN | 23.F26.B22 |
| PLL[1]:CLKOUT1_NOCOUNT | 23.F26.B27 |
| PLL[1]:CLKOUT1_USE_FINE_PS | 23.F26.B28 |
| PLL[1]:CLKOUT2_EDGE | 23.F27.B43 |
| PLL[1]:CLKOUT2_EN | 23.F26.B38 |
| PLL[1]:CLKOUT2_NOCOUNT | 23.F26.B43 |
| PLL[1]:CLKOUT2_USE_FINE_PS | 23.F26.B44 |
| PLL[1]:CLKOUT3_EDGE | 23.F27.B59 |
| PLL[1]:CLKOUT3_EN | 23.F26.B54 |
| PLL[1]:CLKOUT3_NOCOUNT | 23.F26.B59 |
| PLL[1]:CLKOUT3_USE_FINE_PS | 23.F26.B60 |
| PLL[1]:CLKOUT4_CASCADE | 24.F27.B12 |
| PLL[1]:CLKOUT4_EDGE | 24.F27.B11 |
| PLL[1]:CLKOUT4_EN | 24.F26.B6 |
| PLL[1]:CLKOUT4_NOCOUNT | 24.F26.B11 |
| PLL[1]:CLKOUT4_USE_FINE_PS | 24.F26.B12 |
| PLL[1]:CLKOUT5_EDGE | 22.F27.B59 |
| PLL[1]:CLKOUT5_EN | 22.F26.B54 |
| PLL[1]:CLKOUT5_FRAC_WF | 22.F26.B61 |
| PLL[1]:CLKOUT5_NOCOUNT | 22.F26.B59 |
| PLL[1]:CLKOUT5_USE_FINE_PS | 22.F26.B60 |
| PLL[1]:CLKOUT6_EDGE | 24.F27.B27 |
| PLL[1]:CLKOUT6_EN | 24.F26.B22 |
| PLL[1]:CLKOUT6_FRAC_WF | 24.F26.B29 |
| PLL[1]:CLKOUT6_NOCOUNT | 24.F26.B27 |
| PLL[1]:CLKOUT6_USE_FINE_PS | 24.F26.B28 |
| PLL[1]:CLOCK_HOLD | 36.F27.B32 |
| PLL[1]:CP_BIAS_TRIP_SET | 31.F27.B51 |
| PLL[1]:DIRECT_PATH_CNTRL | 22.F27.B41 |
| PLL[1]:DIVCLK_EDGE | 24.F27.B54 |
| PLL[1]:DIVCLK_NOCOUNT | 24.F26.B54 |
| PLL[1]:EN_VCO_DIV1 | 26.F27.B16 |
| PLL[1]:EN_VCO_DIV6 | 26.F26.B16 |
| PLL[1]:GTS_WAIT | 36.F27.B33 |
| PLL[1]:HVLF_CNT_TEST_EN | 25.F27.B27 |
| PLL[1]:HVLF_STEP | 25.F26.B27 |
| PLL[1]:IN_DLY_EN | 22.F27.B47 |
| PLL[1]:MMCM_EN | 36.F26.B32 |
| PLL[1]:STARTUP_WAIT | 36.F26.B33 |
| PLL[1]:VLF_HIGH_DIS_B | 30.F27.B19 |
| PLL[1]:VLF_HIGH_PWDN_B | 30.F26.B48 |
| non-inverted | [0] |
| PLL[0]:CLKFBIN_HT | 15.F27.B2 | 15.F26.B2 | 15.F27.B3 | 15.F26.B3 | 15.F27.B4 | 15.F26.B4 |
|---|---|---|---|---|---|---|
| PLL[0]:CLKFBIN_LT | 15.F27.B5 | 15.F26.B5 | 15.F27.B6 | 15.F26.B6 | 15.F27.B7 | 15.F26.B7 |
| PLL[0]:CLKFBOUT_DT | 15.F27.B21 | 15.F26.B21 | 15.F27.B22 | 15.F26.B22 | 15.F27.B23 | 15.F26.B23 |
| PLL[0]:CLKFBOUT_HT | 15.F27.B26 | 15.F26.B26 | 15.F27.B27 | 15.F26.B27 | 15.F27.B28 | 15.F26.B28 |
| PLL[0]:CLKFBOUT_LT | 15.F27.B29 | 15.F26.B29 | 15.F27.B30 | 15.F26.B30 | 15.F27.B31 | 15.F26.B31 |
| PLL[0]:CLKOUT0_DT | 16.F27.B53 | 16.F26.B53 | 16.F27.B54 | 16.F26.B54 | 16.F27.B55 | 16.F26.B55 |
| PLL[0]:CLKOUT0_HT | 16.F27.B58 | 16.F26.B58 | 16.F27.B59 | 16.F26.B59 | 16.F27.B60 | 16.F26.B60 |
| PLL[0]:CLKOUT0_LT | 16.F27.B61 | 16.F26.B61 | 16.F27.B62 | 16.F26.B62 | 16.F27.B63 | 16.F26.B63 |
| PLL[0]:CLKOUT1_DT | 16.F27.B37 | 16.F26.B37 | 16.F27.B38 | 16.F26.B38 | 16.F27.B39 | 16.F26.B39 |
| PLL[0]:CLKOUT1_HT | 16.F27.B42 | 16.F26.B42 | 16.F27.B43 | 16.F26.B43 | 16.F27.B44 | 16.F26.B44 |
| PLL[0]:CLKOUT1_LT | 16.F27.B45 | 16.F26.B45 | 16.F27.B46 | 16.F26.B46 | 16.F27.B47 | 16.F26.B47 |
| PLL[0]:CLKOUT2_DT | 16.F27.B21 | 16.F26.B21 | 16.F27.B22 | 16.F26.B22 | 16.F27.B23 | 16.F26.B23 |
| PLL[0]:CLKOUT2_HT | 16.F27.B26 | 16.F26.B26 | 16.F27.B27 | 16.F26.B27 | 16.F27.B28 | 16.F26.B28 |
| PLL[0]:CLKOUT2_LT | 16.F27.B29 | 16.F26.B29 | 16.F27.B30 | 16.F26.B30 | 16.F27.B31 | 16.F26.B31 |
| PLL[0]:CLKOUT3_DT | 16.F27.B5 | 16.F26.B5 | 16.F27.B6 | 16.F26.B6 | 16.F27.B7 | 16.F26.B7 |
| PLL[0]:CLKOUT3_HT | 16.F27.B10 | 16.F26.B10 | 16.F27.B11 | 16.F26.B11 | 16.F27.B12 | 16.F26.B12 |
| PLL[0]:CLKOUT3_LT | 16.F27.B13 | 16.F26.B13 | 16.F27.B14 | 16.F26.B14 | 16.F27.B15 | 16.F26.B15 |
| PLL[0]:CLKOUT4_DT | 15.F27.B53 | 15.F26.B53 | 15.F27.B54 | 15.F26.B54 | 15.F27.B55 | 15.F26.B55 |
| PLL[0]:CLKOUT4_HT | 15.F27.B58 | 15.F26.B58 | 15.F27.B59 | 15.F26.B59 | 15.F27.B60 | 15.F26.B60 |
| PLL[0]:CLKOUT4_LT | 15.F27.B61 | 15.F26.B61 | 15.F27.B62 | 15.F26.B62 | 15.F27.B63 | 15.F26.B63 |
| PLL[0]:CLKOUT5_DT | 17.F27.B5 | 17.F26.B5 | 17.F27.B6 | 17.F26.B6 | 17.F27.B7 | 17.F26.B7 |
| PLL[0]:CLKOUT5_HT | 17.F27.B10 | 17.F26.B10 | 17.F27.B11 | 17.F26.B11 | 17.F27.B12 | 17.F26.B12 |
| PLL[0]:CLKOUT5_LT | 17.F27.B13 | 17.F26.B13 | 17.F27.B14 | 17.F26.B14 | 17.F27.B15 | 17.F26.B15 |
| PLL[0]:CLKOUT6_DT | 15.F27.B37 | 15.F26.B37 | 15.F27.B38 | 15.F26.B38 | 15.F27.B39 | 15.F26.B39 |
| PLL[0]:CLKOUT6_HT | 15.F27.B42 | 15.F26.B42 | 15.F27.B43 | 15.F26.B43 | 15.F27.B44 | 15.F26.B44 |
| PLL[0]:CLKOUT6_LT | 15.F27.B45 | 15.F26.B45 | 15.F27.B46 | 15.F26.B46 | 15.F27.B47 | 15.F26.B47 |
| PLL[0]:DIVCLK_HT | 15.F27.B10 | 15.F26.B10 | 15.F27.B11 | 15.F26.B11 | 15.F27.B12 | 15.F26.B12 |
| PLL[0]:DIVCLK_LT | 15.F27.B13 | 15.F26.B13 | 15.F27.B14 | 15.F26.B14 | 15.F27.B15 | 15.F26.B15 |
| PLL[0]:FINE_PS_FRAC | 3.F26.B26 | 3.F27.B27 | 3.F26.B27 | 3.F27.B28 | 3.F26.B28 | 3.F27.B29 |
| PLL[0]:HVLF_CNT_TEST | 14.F27.B37 | 14.F26.B37 | 14.F27.B38 | 14.F26.B38 | 14.F27.B39 | 14.F26.B39 |
| PLL[0]:IN_DLY_MX_CVDD | 17.F27.B58 | 17.F26.B58 | 17.F27.B59 | 17.F26.B59 | 17.F27.B60 | 17.F26.B60 |
| PLL[0]:IN_DLY_MX_DVDD | 17.F27.B19 | 17.F26.B19 | 17.F27.B20 | 17.F26.B20 | 17.F27.B21 | 17.F26.B21 |
| PLL[1]:CLKFBIN_HT | 24.F27.B61 | 24.F26.B61 | 24.F27.B60 | 24.F26.B60 | 24.F27.B59 | 24.F26.B59 |
| PLL[1]:CLKFBIN_LT | 24.F27.B58 | 24.F26.B58 | 24.F27.B57 | 24.F26.B57 | 24.F27.B56 | 24.F26.B56 |
| PLL[1]:CLKFBOUT_DT | 24.F27.B42 | 24.F26.B42 | 24.F27.B41 | 24.F26.B41 | 24.F27.B40 | 24.F26.B40 |
| PLL[1]:CLKFBOUT_HT | 24.F27.B37 | 24.F26.B37 | 24.F27.B36 | 24.F26.B36 | 24.F27.B35 | 24.F26.B35 |
| PLL[1]:CLKFBOUT_LT | 24.F27.B34 | 24.F26.B34 | 24.F27.B33 | 24.F26.B33 | 24.F27.B32 | 24.F26.B32 |
| PLL[1]:CLKOUT0_DT | 23.F27.B10 | 23.F26.B10 | 23.F27.B9 | 23.F26.B9 | 23.F27.B8 | 23.F26.B8 |
| PLL[1]:CLKOUT0_HT | 23.F27.B5 | 23.F26.B5 | 23.F27.B4 | 23.F26.B4 | 23.F27.B3 | 23.F26.B3 |
| PLL[1]:CLKOUT0_LT | 23.F27.B2 | 23.F26.B2 | 23.F27.B1 | 23.F26.B1 | 23.F27.B0 | 23.F26.B0 |
| PLL[1]:CLKOUT1_DT | 23.F27.B26 | 23.F26.B26 | 23.F27.B25 | 23.F26.B25 | 23.F27.B24 | 23.F26.B24 |
| PLL[1]:CLKOUT1_HT | 23.F27.B21 | 23.F26.B21 | 23.F27.B20 | 23.F26.B20 | 23.F27.B19 | 23.F26.B19 |
| PLL[1]:CLKOUT1_LT | 23.F27.B18 | 23.F26.B18 | 23.F27.B17 | 23.F26.B17 | 23.F27.B16 | 23.F26.B16 |
| PLL[1]:CLKOUT2_DT | 23.F27.B42 | 23.F26.B42 | 23.F27.B41 | 23.F26.B41 | 23.F27.B40 | 23.F26.B40 |
| PLL[1]:CLKOUT2_HT | 23.F27.B37 | 23.F26.B37 | 23.F27.B36 | 23.F26.B36 | 23.F27.B35 | 23.F26.B35 |
| PLL[1]:CLKOUT2_LT | 23.F27.B34 | 23.F26.B34 | 23.F27.B33 | 23.F26.B33 | 23.F27.B32 | 23.F26.B32 |
| PLL[1]:CLKOUT3_DT | 23.F27.B58 | 23.F26.B58 | 23.F27.B57 | 23.F26.B57 | 23.F27.B56 | 23.F26.B56 |
| PLL[1]:CLKOUT3_HT | 23.F27.B53 | 23.F26.B53 | 23.F27.B52 | 23.F26.B52 | 23.F27.B51 | 23.F26.B51 |
| PLL[1]:CLKOUT3_LT | 23.F27.B50 | 23.F26.B50 | 23.F27.B49 | 23.F26.B49 | 23.F27.B48 | 23.F26.B48 |
| PLL[1]:CLKOUT4_DT | 24.F27.B10 | 24.F26.B10 | 24.F27.B9 | 24.F26.B9 | 24.F27.B8 | 24.F26.B8 |
| PLL[1]:CLKOUT4_HT | 24.F27.B5 | 24.F26.B5 | 24.F27.B4 | 24.F26.B4 | 24.F27.B3 | 24.F26.B3 |
| PLL[1]:CLKOUT4_LT | 24.F27.B2 | 24.F26.B2 | 24.F27.B1 | 24.F26.B1 | 24.F27.B0 | 24.F26.B0 |
| PLL[1]:CLKOUT5_DT | 22.F27.B58 | 22.F26.B58 | 22.F27.B57 | 22.F26.B57 | 22.F27.B56 | 22.F26.B56 |
| PLL[1]:CLKOUT5_HT | 22.F27.B53 | 22.F26.B53 | 22.F27.B52 | 22.F26.B52 | 22.F27.B51 | 22.F26.B51 |
| PLL[1]:CLKOUT5_LT | 22.F27.B50 | 22.F26.B50 | 22.F27.B49 | 22.F26.B49 | 22.F27.B48 | 22.F26.B48 |
| PLL[1]:CLKOUT6_DT | 24.F27.B26 | 24.F26.B26 | 24.F27.B25 | 24.F26.B25 | 24.F27.B24 | 24.F26.B24 |
| PLL[1]:CLKOUT6_HT | 24.F27.B21 | 24.F26.B21 | 24.F27.B20 | 24.F26.B20 | 24.F27.B19 | 24.F26.B19 |
| PLL[1]:CLKOUT6_LT | 24.F27.B18 | 24.F26.B18 | 24.F27.B17 | 24.F26.B17 | 24.F27.B16 | 24.F26.B16 |
| PLL[1]:DIVCLK_HT | 24.F27.B53 | 24.F26.B53 | 24.F27.B52 | 24.F26.B52 | 24.F27.B51 | 24.F26.B51 |
| PLL[1]:DIVCLK_LT | 24.F27.B50 | 24.F26.B50 | 24.F27.B49 | 24.F26.B49 | 24.F27.B48 | 24.F26.B48 |
| PLL[1]:FINE_PS_FRAC | 36.F26.B37 | 36.F27.B36 | 36.F26.B36 | 36.F27.B35 | 36.F26.B35 | 36.F27.B34 |
| PLL[1]:HVLF_CNT_TEST | 25.F27.B26 | 25.F26.B26 | 25.F27.B25 | 25.F26.B25 | 25.F27.B24 | 25.F26.B24 |
| PLL[1]:IN_DLY_MX_CVDD | 22.F27.B5 | 22.F26.B5 | 22.F27.B4 | 22.F26.B4 | 22.F27.B3 | 22.F26.B3 |
| PLL[1]:IN_DLY_MX_DVDD | 22.F27.B44 | 22.F26.B44 | 22.F27.B43 | 22.F26.B43 | 22.F27.B42 | 22.F26.B42 |
| non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
| PLL[0]:CONTROL_0 | 3.F27.B8 | 3.F26.B8 | 3.F27.B9 | 3.F26.B9 | 3.F27.B10 | 3.F26.B10 | 3.F27.B11 | 3.F26.B11 | 3.F27.B12 | 3.F26.B12 | 3.F27.B13 | 3.F26.B13 | 3.F27.B14 | 3.F26.B14 | 3.F27.B15 | 3.F26.B15 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PLL[0]:CONTROL_1 | 3.F27.B0 | 3.F26.B0 | 3.F27.B1 | 3.F26.B1 | 3.F27.B2 | 3.F26.B2 | 3.F27.B3 | 3.F26.B3 | 3.F27.B4 | 3.F26.B4 | 3.F27.B5 | 3.F26.B5 | 3.F27.B6 | 3.F26.B6 | 3.F27.B7 | 3.F26.B7 |
| PLL[0]:CONTROL_2 | 2.F27.B56 | 2.F26.B56 | 2.F27.B57 | 2.F26.B57 | 2.F27.B58 | 2.F26.B58 | 2.F27.B59 | 2.F26.B59 | 2.F27.B60 | 2.F26.B60 | 2.F27.B61 | 2.F26.B61 | 2.F27.B62 | 2.F26.B62 | 2.F27.B63 | 2.F26.B63 |
| PLL[0]:CONTROL_3 | 2.F27.B48 | 2.F26.B48 | 2.F27.B49 | 2.F26.B49 | 2.F27.B50 | 2.F26.B50 | 2.F27.B51 | 2.F26.B51 | 2.F27.B52 | 2.F26.B52 | 2.F27.B53 | 2.F26.B53 | 2.F27.B54 | 2.F26.B54 | 2.F27.B55 | 2.F26.B55 |
| PLL[0]:CONTROL_4 | 2.F27.B40 | 2.F26.B40 | 2.F27.B41 | 2.F26.B41 | 2.F27.B42 | 2.F26.B42 | 2.F27.B43 | 2.F26.B43 | 2.F27.B44 | 2.F26.B44 | 2.F27.B45 | 2.F26.B45 | 2.F27.B46 | 2.F26.B46 | 2.F27.B47 | 2.F26.B47 |
| PLL[0]:CONTROL_5 | 2.F27.B32 | 2.F26.B32 | 2.F27.B33 | 2.F26.B33 | 2.F27.B34 | 2.F26.B34 | 2.F27.B35 | 2.F26.B35 | 2.F27.B36 | 2.F26.B36 | 2.F27.B37 | 2.F26.B37 | 2.F27.B38 | 2.F26.B38 | 2.F27.B39 | 2.F26.B39 |
| PLL[1]:CONTROL_0 | 36.F27.B55 | 36.F26.B55 | 36.F27.B54 | 36.F26.B54 | 36.F27.B53 | 36.F26.B53 | 36.F27.B52 | 36.F26.B52 | 36.F27.B51 | 36.F26.B51 | 36.F27.B50 | 36.F26.B50 | 36.F27.B49 | 36.F26.B49 | 36.F27.B48 | 36.F26.B48 |
| PLL[1]:CONTROL_1 | 36.F27.B63 | 36.F26.B63 | 36.F27.B62 | 36.F26.B62 | 36.F27.B61 | 36.F26.B61 | 36.F27.B60 | 36.F26.B60 | 36.F27.B59 | 36.F26.B59 | 36.F27.B58 | 36.F26.B58 | 36.F27.B57 | 36.F26.B57 | 36.F27.B56 | 36.F26.B56 |
| PLL[1]:CONTROL_2 | 37.F27.B7 | 37.F26.B7 | 37.F27.B6 | 37.F26.B6 | 37.F27.B5 | 37.F26.B5 | 37.F27.B4 | 37.F26.B4 | 37.F27.B3 | 37.F26.B3 | 37.F27.B2 | 37.F26.B2 | 37.F27.B1 | 37.F26.B1 | 37.F27.B0 | 37.F26.B0 |
| PLL[1]:CONTROL_3 | 37.F27.B15 | 37.F26.B15 | 37.F27.B14 | 37.F26.B14 | 37.F27.B13 | 37.F26.B13 | 37.F27.B12 | 37.F26.B12 | 37.F27.B11 | 37.F26.B11 | 37.F27.B10 | 37.F26.B10 | 37.F27.B9 | 37.F26.B9 | 37.F27.B8 | 37.F26.B8 |
| PLL[1]:CONTROL_4 | 37.F27.B23 | 37.F26.B23 | 37.F27.B22 | 37.F26.B22 | 37.F27.B21 | 37.F26.B21 | 37.F27.B20 | 37.F26.B20 | 37.F27.B19 | 37.F26.B19 | 37.F27.B18 | 37.F26.B18 | 37.F27.B17 | 37.F26.B17 | 37.F27.B16 | 37.F26.B16 |
| PLL[1]:CONTROL_5 | 37.F27.B31 | 37.F26.B31 | 37.F27.B30 | 37.F26.B30 | 37.F27.B29 | 37.F26.B29 | 37.F27.B28 | 37.F26.B28 | 37.F27.B27 | 37.F26.B27 | 37.F27.B26 | 37.F26.B26 | 37.F27.B25 | 37.F26.B25 | 37.F27.B24 | 37.F26.B24 |
| non-inverted | [15] | [14] | [13] | [12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PLL[0]:INTERP_EN | 12.F27.B56 | 12.F26.B57 | 12.F27.B58 | 12.F26.B59 | 12.F27.B60 | 12.F26.B61 | 12.F27.B62 | 12.F26.B63 |
|---|---|---|---|---|---|---|---|---|
| PLL[1]:INTERP_EN | 27.F27.B7 | 27.F26.B6 | 27.F27.B5 | 27.F26.B4 | 27.F27.B3 | 27.F26.B2 | 27.F27.B1 | 27.F26.B0 |
| non-inverted | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PLL[0]:IN_DLY_SET | 17.F26.B16 | 17.F27.B17 | 17.F26.B17 | 17.F27.B18 | 17.F26.B18 |
|---|---|---|---|---|---|
| PLL[0]:LOCK_FB_DLY | 14.F26.B48 | 14.F27.B49 | 14.F26.B49 | 14.F27.B50 | 14.F26.B50 |
| PLL[0]:LOCK_REF_DLY | 14.F26.B40 | 14.F27.B41 | 14.F26.B41 | 14.F27.B42 | 14.F26.B42 |
| PLL[1]:IN_DLY_SET | 22.F26.B47 | 22.F27.B46 | 22.F26.B46 | 22.F27.B45 | 22.F26.B45 |
| PLL[1]:LOCK_FB_DLY | 25.F26.B15 | 25.F27.B14 | 25.F26.B14 | 25.F27.B13 | 25.F26.B13 |
| PLL[1]:LOCK_REF_DLY | 25.F26.B23 | 25.F27.B22 | 25.F26.B22 | 25.F27.B21 | 25.F26.B21 |
| non-inverted | [4] | [3] | [2] | [1] | [0] |
| PLL[0]:LOCK_CNT | 14.F27.B59 | 14.F26.B59 | 14.F27.B60 | 14.F26.B60 | 14.F27.B61 | 14.F26.B61 | 14.F27.B62 | 14.F26.B62 | 14.F27.B63 | 14.F26.B63 |
|---|---|---|---|---|---|---|---|---|---|---|
| PLL[0]:LOCK_SAT_HIGH | 14.F27.B43 | 14.F26.B43 | 14.F27.B44 | 14.F26.B44 | 14.F27.B45 | 14.F26.B45 | 14.F27.B46 | 14.F26.B46 | 14.F27.B47 | 14.F26.B47 |
| PLL[0]:UNLOCK_CNT | 14.F27.B51 | 14.F26.B51 | 14.F27.B52 | 14.F26.B52 | 14.F27.B53 | 14.F26.B53 | 14.F27.B54 | 14.F26.B54 | 14.F27.B55 | 14.F26.B55 |
| PLL[1]:LOCK_CNT | 25.F27.B4 | 25.F26.B4 | 25.F27.B3 | 25.F26.B3 | 25.F27.B2 | 25.F26.B2 | 25.F27.B1 | 25.F26.B1 | 25.F27.B0 | 25.F26.B0 |
| PLL[1]:LOCK_SAT_HIGH | 25.F27.B20 | 25.F26.B20 | 25.F27.B19 | 25.F26.B19 | 25.F27.B18 | 25.F26.B18 | 25.F27.B17 | 25.F26.B17 | 25.F27.B16 | 25.F26.B16 |
| PLL[1]:UNLOCK_CNT | 25.F27.B12 | 25.F26.B12 | 25.F27.B11 | 25.F26.B11 | 25.F27.B10 | 25.F26.B10 | 25.F27.B9 | 25.F26.B9 | 25.F27.B8 | 25.F26.B8 |
| non-inverted | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
| PLL[0]:PFD | 14.F26.B18 | 14.F27.B19 | 14.F26.B19 | 14.F27.B20 | 14.F26.B20 | 14.F27.B21 | 14.F26.B21 |
|---|---|---|---|---|---|---|---|
| PLL[1]:PFD | 25.F26.B45 | 25.F27.B44 | 25.F26.B44 | 25.F27.B43 | 25.F26.B43 | 25.F27.B42 | 25.F26.B42 |
| non-inverted | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
Tables
| Name | MMCM:CP | MMCM:RES | MMCM:LFHF |
|---|---|---|---|
| HIGH:1 | 5 | 15 | 0 |
| HIGH:10 | 15 | 10 | 0 |
| HIGH:11 | 15 | 10 | 0 |
| HIGH:12 | 14 | 12 | 0 |
| HIGH:13 | 15 | 12 | 0 |
| HIGH:14 | 15 | 12 | 0 |
| HIGH:15 | 15 | 12 | 0 |
| HIGH:16 | 15 | 12 | 0 |
| HIGH:17 | 15 | 12 | 0 |
| HIGH:18 | 15 | 12 | 0 |
| HIGH:19 | 15 | 12 | 0 |
| HIGH:2 | 15 | 15 | 0 |
| HIGH:20 | 15 | 12 | 0 |
| HIGH:21 | 14 | 12 | 0 |
| HIGH:22 | 14 | 12 | 0 |
| HIGH:23 | 14 | 12 | 0 |
| HIGH:24 | 15 | 10 | 0 |
| HIGH:25 | 13 | 12 | 0 |
| HIGH:26 | 12 | 2 | 0 |
| HIGH:27 | 13 | 12 | 0 |
| HIGH:28 | 13 | 12 | 0 |
| HIGH:29 | 15 | 10 | 0 |
| HIGH:3 | 15 | 13 | 0 |
| HIGH:30 | 15 | 10 | 0 |
| HIGH:31 | 15 | 10 | 0 |
| HIGH:32 | 7 | 2 | 0 |
| HIGH:33 | 12 | 12 | 0 |
| HIGH:34 | 12 | 12 | 0 |
| HIGH:35 | 14 | 10 | 0 |
| HIGH:36 | 6 | 2 | 0 |
| HIGH:37 | 6 | 2 | 0 |
| HIGH:38 | 6 | 2 | 0 |
| HIGH:39 | 7 | 12 | 0 |
| HIGH:4 | 15 | 9 | 0 |
| HIGH:40 | 6 | 2 | 0 |
| HIGH:41 | 4 | 4 | 0 |
| HIGH:42 | 4 | 4 | 0 |
| HIGH:43 | 4 | 4 | 0 |
| HIGH:44 | 4 | 4 | 0 |
| HIGH:45 | 4 | 4 | 0 |
| HIGH:46 | 4 | 4 | 0 |
| HIGH:47 | 3 | 8 | 0 |
| HIGH:48 | 3 | 8 | 0 |
| HIGH:49 | 3 | 8 | 0 |
| HIGH:5 | 15 | 14 | 0 |
| HIGH:50 | 3 | 8 | 0 |
| HIGH:51 | 3 | 8 | 0 |
| HIGH:52 | 3 | 8 | 0 |
| HIGH:53 | 3 | 8 | 0 |
| HIGH:54 | 3 | 8 | 0 |
| HIGH:55 | 3 | 8 | 0 |
| HIGH:56 | 3 | 8 | 0 |
| HIGH:57 | 3 | 8 | 0 |
| HIGH:58 | 3 | 8 | 0 |
| HIGH:59 | 3 | 8 | 0 |
| HIGH:6 | 15 | 1 | 0 |
| HIGH:60 | 3 | 8 | 0 |
| HIGH:61 | 3 | 8 | 0 |
| HIGH:62 | 3 | 8 | 0 |
| HIGH:63 | 3 | 8 | 0 |
| HIGH:64 | 3 | 8 | 0 |
| HIGH:7 | 15 | 1 | 0 |
| HIGH:8 | 15 | 6 | 0 |
| HIGH:9 | 15 | 10 | 0 |
| LOW:1 | 1 | 7 | 3 |
| LOW:10 | 1 | 2 | 3 |
| LOW:11 | 1 | 2 | 3 |
| LOW:12 | 1 | 2 | 3 |
| LOW:13 | 2 | 12 | 3 |
| LOW:14 | 1 | 4 | 3 |
| LOW:15 | 1 | 4 | 3 |
| LOW:16 | 1 | 4 | 3 |
| LOW:17 | 1 | 4 | 3 |
| LOW:18 | 1 | 4 | 3 |
| LOW:19 | 1 | 4 | 3 |
| LOW:2 | 1 | 5 | 3 |
| LOW:20 | 1 | 4 | 3 |
| LOW:21 | 1 | 4 | 3 |
| LOW:22 | 1 | 4 | 3 |
| LOW:23 | 1 | 4 | 3 |
| LOW:24 | 1 | 8 | 3 |
| LOW:25 | 1 | 8 | 3 |
| LOW:26 | 1 | 8 | 3 |
| LOW:27 | 1 | 8 | 3 |
| LOW:28 | 1 | 8 | 3 |
| LOW:29 | 1 | 8 | 3 |
| LOW:3 | 1 | 14 | 3 |
| LOW:30 | 1 | 8 | 3 |
| LOW:31 | 1 | 8 | 3 |
| LOW:32 | 1 | 8 | 3 |
| LOW:33 | 1 | 8 | 3 |
| LOW:34 | 1 | 8 | 3 |
| LOW:35 | 1 | 8 | 3 |
| LOW:36 | 1 | 8 | 3 |
| LOW:37 | 1 | 8 | 3 |
| LOW:38 | 2 | 4 | 3 |
| LOW:39 | 2 | 4 | 3 |
| LOW:4 | 1 | 6 | 3 |
| LOW:40 | 2 | 4 | 3 |
| LOW:41 | 2 | 4 | 3 |
| LOW:42 | 2 | 4 | 3 |
| LOW:43 | 2 | 4 | 3 |
| LOW:44 | 2 | 4 | 3 |
| LOW:45 | 2 | 4 | 3 |
| LOW:46 | 2 | 4 | 3 |
| LOW:47 | 2 | 4 | 3 |
| LOW:48 | 2 | 8 | 3 |
| LOW:49 | 2 | 8 | 3 |
| LOW:5 | 1 | 10 | 3 |
| LOW:50 | 2 | 8 | 3 |
| LOW:51 | 2 | 8 | 3 |
| LOW:52 | 2 | 8 | 3 |
| LOW:53 | 2 | 8 | 3 |
| LOW:54 | 2 | 8 | 3 |
| LOW:55 | 2 | 8 | 3 |
| LOW:56 | 2 | 8 | 3 |
| LOW:57 | 2 | 8 | 3 |
| LOW:58 | 2 | 8 | 3 |
| LOW:59 | 2 | 8 | 3 |
| LOW:6 | 1 | 12 | 3 |
| LOW:60 | 2 | 8 | 3 |
| LOW:61 | 2 | 8 | 3 |
| LOW:62 | 2 | 8 | 3 |
| LOW:63 | 2 | 8 | 3 |
| LOW:64 | 2 | 8 | 3 |
| LOW:7 | 1 | 12 | 3 |
| LOW:8 | 1 | 12 | 3 |
| LOW:9 | 1 | 12 | 3 |
| Name | MMCM:LOCK_REF_DLY | MMCM:LOCK_FB_DLY | MMCM:LOCK_CNT | MMCM:LOCK_SAT_HIGH | MMCM:UNLOCK_CNT |
|---|---|---|---|---|---|
| 1 | 6 | 6 | 1000 | 1001 | 1 |
| 10 | 28 | 28 | 1000 | 1001 | 1 |
| 11 | 31 | 31 | 900 | 1001 | 1 |
| 12 | 31 | 31 | 825 | 1001 | 1 |
| 13 | 31 | 31 | 750 | 1001 | 1 |
| 14 | 31 | 31 | 700 | 1001 | 1 |
| 15 | 31 | 31 | 650 | 1001 | 1 |
| 16 | 31 | 31 | 625 | 1001 | 1 |
| 17 | 31 | 31 | 575 | 1001 | 1 |
| 18 | 31 | 31 | 550 | 1001 | 1 |
| 19 | 31 | 31 | 525 | 1001 | 1 |
| 2 | 6 | 6 | 1000 | 1001 | 1 |
| 20 | 31 | 31 | 500 | 1001 | 1 |
| 21 | 31 | 31 | 475 | 1001 | 1 |
| 22 | 31 | 31 | 450 | 1001 | 1 |
| 23 | 31 | 31 | 425 | 1001 | 1 |
| 24 | 31 | 31 | 400 | 1001 | 1 |
| 25 | 31 | 31 | 400 | 1001 | 1 |
| 26 | 31 | 31 | 375 | 1001 | 1 |
| 27 | 31 | 31 | 350 | 1001 | 1 |
| 28 | 31 | 31 | 350 | 1001 | 1 |
| 29 | 31 | 31 | 325 | 1001 | 1 |
| 3 | 8 | 8 | 1000 | 1001 | 1 |
| 30 | 31 | 31 | 325 | 1001 | 1 |
| 31 | 31 | 31 | 300 | 1001 | 1 |
| 32 | 31 | 31 | 300 | 1001 | 1 |
| 33 | 31 | 31 | 300 | 1001 | 1 |
| 34 | 31 | 31 | 275 | 1001 | 1 |
| 35 | 31 | 31 | 275 | 1001 | 1 |
| 36 | 31 | 31 | 275 | 1001 | 1 |
| 37 | 31 | 31 | 250 | 1001 | 1 |
| 38 | 31 | 31 | 250 | 1001 | 1 |
| 39 | 31 | 31 | 250 | 1001 | 1 |
| 4 | 11 | 11 | 1000 | 1001 | 1 |
| 40 | 31 | 31 | 250 | 1001 | 1 |
| 41 | 31 | 31 | 250 | 1001 | 1 |
| 42 | 31 | 31 | 250 | 1001 | 1 |
| 43 | 31 | 31 | 250 | 1001 | 1 |
| 44 | 31 | 31 | 250 | 1001 | 1 |
| 45 | 31 | 31 | 250 | 1001 | 1 |
| 46 | 31 | 31 | 250 | 1001 | 1 |
| 47 | 31 | 31 | 250 | 1001 | 1 |
| 48 | 31 | 31 | 250 | 1001 | 1 |
| 49 | 31 | 31 | 250 | 1001 | 1 |
| 5 | 14 | 14 | 1000 | 1001 | 1 |
| 50 | 31 | 31 | 250 | 1001 | 1 |
| 51 | 31 | 31 | 250 | 1001 | 1 |
| 52 | 31 | 31 | 250 | 1001 | 1 |
| 53 | 31 | 31 | 250 | 1001 | 1 |
| 54 | 31 | 31 | 250 | 1001 | 1 |
| 55 | 31 | 31 | 250 | 1001 | 1 |
| 56 | 31 | 31 | 250 | 1001 | 1 |
| 57 | 31 | 31 | 250 | 1001 | 1 |
| 58 | 31 | 31 | 250 | 1001 | 1 |
| 59 | 31 | 31 | 250 | 1001 | 1 |
| 6 | 17 | 17 | 1000 | 1001 | 1 |
| 60 | 31 | 31 | 250 | 1001 | 1 |
| 61 | 31 | 31 | 250 | 1001 | 1 |
| 62 | 31 | 31 | 250 | 1001 | 1 |
| 63 | 31 | 31 | 250 | 1001 | 1 |
| 64 | 31 | 31 | 250 | 1001 | 1 |
| 7 | 19 | 19 | 1000 | 1001 | 1 |
| 8 | 22 | 22 | 1000 | 1001 | 1 |
| 9 | 25 | 25 | 1000 | 1001 | 1 |
| Device | MMCM:IN_DLY_SET | ||||
|---|---|---|---|---|---|
| [4] | [3] | [2] | [1] | [0] | |
| xc6vlx760 | 1 | 1 | 1 | 1 | 1 |
| xc6vlx760l | 1 | 1 | 1 | 1 | 1 |
| xc6vlx75t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx75tl | 1 | 1 | 0 | 0 | 0 |
| xc6vcx75t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx130t | 1 | 1 | 0 | 0 | 0 |
| xq6vlx130t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx130tl | 1 | 1 | 0 | 0 | 0 |
| xq6vlx130tl | 1 | 1 | 0 | 0 | 0 |
| xc6vcx130t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx195t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx195tl | 1 | 1 | 0 | 0 | 0 |
| xc6vcx195t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx240t | 1 | 1 | 0 | 0 | 0 |
| xq6vlx240t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx240tl | 1 | 1 | 0 | 0 | 0 |
| xq6vlx240tl | 1 | 1 | 0 | 0 | 0 |
| xc6vcx240t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx365t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx365tl | 1 | 1 | 0 | 0 | 0 |
| xc6vlx550t | 1 | 1 | 0 | 0 | 0 |
| xq6vlx550t | 1 | 1 | 0 | 0 | 0 |
| xc6vlx550tl | 1 | 1 | 0 | 0 | 0 |
| xq6vlx550tl | 1 | 1 | 0 | 0 | 0 |
| xc6vsx315t | 1 | 1 | 0 | 0 | 0 |
| xq6vsx315t | 1 | 1 | 0 | 0 | 0 |
| xc6vsx315tl | 1 | 1 | 0 | 0 | 0 |
| xq6vsx315tl | 1 | 1 | 0 | 0 | 0 |
| xc6vsx475t | 1 | 1 | 0 | 0 | 0 |
| xq6vsx475t | 1 | 1 | 0 | 0 | 0 |
| xc6vsx475tl | 1 | 1 | 0 | 0 | 0 |
| xq6vsx475tl | 1 | 1 | 0 | 0 | 0 |
| xc6vhx250t | 1 | 1 | 0 | 0 | 0 |
| xc6vhx255t | 1 | 1 | 0 | 0 | 0 |
| xc6vhx380t | 1 | 1 | 0 | 0 | 0 |
| xc6vhx565t | 1 | 1 | 0 | 0 | 0 |